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ADP1048ARQZ-R7 数据表(PDF) 70 Page - Analog Devices |
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ADP1048ARQZ-R7 数据表(HTML) 70 Page - Analog Devices |
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70 / 84 page  ADP1047/ADP1048 Data Sheet Rev. 0 | Page 70 of 84 CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT REGISTER Table 102. Register 0xFE29—Current Loop Filter Gain for Low Line Input Bits Bit Name R/W Description [7:0] Current loop filter gain for low line R/W These bits set the current loop digital filter gain of the PFC current loop under the low line input voltage. CURRENT LOOP FILTER ZERO FOR LOW LINE INPUT REGISTER Table 103. Register 0xFE2A—Current Loop Filter Zero for Low Line Input Bits Bit Name R/W Description [7:0] Current loop filter zero for low line R/W These bits set the current loop digital filter zero of the PFC current loop under the low line input voltage. CURRENT LOOP FILTER GAIN FOR HIGH LINE INPUT REGISTER Table 104. Register 0xFE2B—Current Loop Filter Gain for High Line Input Bits Bit Name R/W Description [7:0] Current loop filter gain for high line R/W These bits set the current loop digital filter gain of the PFC current loop under the high line input voltage. CURRENT LOOP FILTER ZERO FOR HIGH LINE INPUT REGISTER Table 105. Register 0xFE2C—Current Loop Filter Zero for High Line Input Bits Bit Name R/W Description [7:0] Current loop filter zero for high line R/W These bits set the current loop digital filter zero of the PFC current loop under the high line input voltage. SOFT START SET REGISTER Table 106. Register 0xFE2D—Soft Start Set Bits Bit Name R/W Description [7:6] RSVD R Reserved. [5:3] Soft start delay time R/W These bits set the delay time between the inrush signal and the beginning of the soft start. Bit 5 Bit 4 Bit 3 Number of Full AC Line Cycles 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 [2:0] Soft start time R/W These bits set the soft start time. Bit 2 Bit 1 Bit 0 Time 0 0 0 112 ms 0 0 1 168 ms 0 1 0 224 ms 0 1 1 280 ms 1 0 0 392 ms 1 0 1 504 ms 1 1 0 616 ms 1 1 1 728 ms |
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