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数据搜索系统，热门电子元器件搜索 |
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WM8904ECS/R 数据表(PDF) 133 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 133 Page - Wolfson Microelectronics plc |
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133 / 188 page  Pre-Production WM8904 w PP, Rev 3.3, September 2012 133 POWER-ON RESET The WM8904 includes an internal Power-On-Reset (POR) circuit, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DCVDD. The internal POR ¯¯¯ signal is asserted low when AVDD or DCVDD are below minimum thresholds. The specific behaviour of the circuit will vary, depending on the relative timing of the supply voltages. Typical scenarios are illustrated in Figure 69 and Figure 70. DCVDD Vpord_on 0V AVDD 0V Vpora Vpora_off LO HI Internal POR Device ready POR active POR active POR undefined Figure 69 Power On Reset timing - AVDD enabled first DCVDD 0V AVDD 0V Vpora Vpord_off LO HI Internal POR Device ready Vpora_on POR active POR active POR undefined Figure 70 Power On Reset timing - DCVDD enabled first |
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