WM8321 datasheet(107/253 Pages) WOLFSON

107 / 253 page

Production Data

WM8321

PD, February 2012, Rev 4.0

107

20.4 DIGITAL RIGHTS MANAGEMENT

The Real Time Clock (RTC) maintains a continuous record of the time; this is maintained at all times,

including when the WM8321 is powered down and the RTC function is maintained by the backup

battery.

It is highly desirable to be able to write to the RTC counter in order to configure it for logical

translation into hours/minutes and to support calendar functions. However, for digital rights

management purposes, it is important that malicious modification of the RTC is either prevented or

detected.

The security measure implemented on the WM8321 is the RTC Write Counter. This register is

initialised to 0000h during Power On Reset, and is updated automatically whenever a Write operation

is scheduled on either of the RTC_TIME registers. Note that, when the RTC Write Counter is updated,

the new value is generated at random; it is not a sequential counter.

It is assumed that legitimate updates to the RTC_TIME are only those initiated by the Application

Processor (AP). When the AP makes an update to the RTC_TIME, the AP can also read the new

value of the RTC Write Counter, and should store the value in non-volatile memory. If the AP detects

a change in value of the RTC Write Counter, and this was not caused by the AP itself writing to the

RTC_TIME, this means that an unauthorised write to the RTC_TIME registers has occurred.

In order to make it difficult for an unauthorised RTC_TIME update to be masked by simply writing to

the RTC Write Counter, the RTC_WR_CNT field is generated at random by the WM8321 whenever

the RTC_TIME field is updated.

For additional security, the WM8321 does not allow the RTC to be updated more than 8 times in a

one-hour period. Additional write attempts will be ignored.

The RTC Control registers are described in Table 49.

20.5 BACKUP MODE CLOCKING OPTIONS

The BACKUP state is entered when the PVDD power supply is below the reset threshold of the

device. Typically, this means that the PVDD supply has been removed. Most of the device functions

and registers are reset in this state.

The RTC and oscillator and a ‘software scratch’ memory area can be maintained from a backup

power source in the BACKUP state. This is provided using a coin cell, super/gold capacitor, or else a

standard capacitor, connected to the LDO12VOUT pin via a 22kΩ resistor. See Section 17.3 for

further details.

The RTC and oscillator can be disabled in the BACKUP state by setting the XTAL_BKUPENA register

bit to 0. This feature may be used to minimise the device power consumption in the BACKUP state. A

F capacitor connected to LDO12VOUT can maintain the RTC value, unclocked, for up to 5

minutes in BACKUP if the oscillator is disabled.

The XTAL_BKUPENA register bit is defined in Section 13.1. For more details on backup power, see

Section 17.3.

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