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WM8321 数据表(PDF) 108 Page - Wolfson Microelectronics plc |
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WM8321 数据表(HTML) 108 Page - Wolfson Microelectronics plc |
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108 / 253 page  WM8321 Production Data w PD, February 2012, Rev 4.0 108 21 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) 21.1 GENERAL DESCRIPTION The WM8321 has 12 general-purpose input/output (GPIO) pins, GPIO1 - GPIO12. These can be configured as inputs or outputs, active high or active low, with optional on-chip pull-up or pull-down resistors. GPIO outputs can either be CMOS driven or Open Drain configuration. Each GPIO pin can be tri-stated and can also be used to trigger Interrupts. The function of each GPIO pin is selected individually. Different voltage power domains are selectable on a pin by pin basis for GPIOs 1-12. Input de-bounce is automatically implemented on selected GPIO functions. Note that, when GPIO10, GPIO11 or GPIO12 is used as an input to the AUXADC (see Section 18), then the normal GPIO functionality cannot be supported on the affected pin(s). It is recommended that the respective GPIO(s) are tri-stated, as described in Section 21.3. 21.2 GPIO FUNCTIONS The list of GPIO functions supported by the WM8321 is contained in Table 52 (for input functions) and Table 53 (for output functions). The input functions are selected when the respective GPn_DIR register bit is 1. The output functions are selected when the respective GPn_DIR register bit is 0. The selected function for each GPIO pin is selected by writing to the respective GPn_FN register bits. All functions are available on all GPIO pins. The polarity of each input or output GPIO function can be selected using the applicable GPn_POL register bit. The available power domains for each pin are specific to different GPIOs. The de-bounce time for the GPIO input functions is determined by the GPn_FN field. Some of the input functions allow a choice of de-bounce times, as detailed in Table 52. The register controls for configuring the GPIO pins are defined in Section 21.3. GPn_FN GPIO INPUT FUNCTION DESCRIPTION DE-BOUNCE TIME 0h GPIO GPIO input. Logic level is read from the GPn_LVL register bits. See Section 21.3. 32 s to 64s 1h 4ms to 8ms 2h ON/OFF Request Control input for requesting an ON/OFF state transition. See Section 11.3. Under default polarity (GPn_POL=1), a rising edge requests the ON state and a falling edge requests the OFF state. 32ms 64ms 3h SLEEP/WAKE Request Control input for requesting a SLEEP/WAKE state transition. See Section 11.3. Under default polarity (GPn_POL=1), a rising edge requests the SLEEP state and a falling edge requests the WAKE transition to the ON state. 32 s to 64s 4h 32ms to 64ms 5h SLEEP Request Control input for requesting a SLEEP state transition. See Section 11.3. Under default polarity (GPn_POL=1), a rising edge requests the SLEEP state and a falling edge has no effect. 32 s to 64s 6h ON Request Control input for requesting an ON state transition. See Section 11.3. Under default polarity (GPn_POL=1), a rising edge requests the ON state and a falling edge has no effect. 32 s to 64s 7h Watchdog Reset Control input for resetting the Watchdog Timer. See Section 25. 32 s to 64s |
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