ST7LITE25F2 datasheet(56/166 Pages) STMICROELECTRONICS

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Power saving modes

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Doc ID 8349 Rev 5

Figure 25. HALT mode flowchart

WDGHALT is an option bit (see Section 15.1: Option bytes for more details).

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to

Table 12: Interrupt mapping for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

If the PLL is enabled by option byte, it outputs the clock after a delay of tSTARTUP (see Figure 12: PLL

output frequency timing diagram).

9.4.1

HALT mode recommendations

●

Make sure that an external event is available to wake up the microcontroller from Halt

mode.

●

When using an external interrupt to wake up the microcontroller, reinitialize the

corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT

Reset

Interrupt (3)

CPU

Oscillator

Peripherals (2)

Ibit

OFF

Fetch reset vector

or service interrupt

CPU

Oscillator

Peripherals

Ibit

OFF

X 4)

CPU

Oscillator

Peripherals

Ibit

X 4)

256 or 4096 CPU clock

delay(5)

Watchdog

ENABLE

DISABLE

WDGHALT (1)

Watchdog

reset

cycle

HALT instruction

(ACTIVE-HALT disabled)

(AWUCSR.AWUEN=0)

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