ST7LITE25F2 datasheet(43/166 Pages) STMICROELECTRONICS

部件名	ST7LITE25F2

功能描述	8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, Timers, SPI

PDF	166 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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43 / 166 page

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

Supply, reset and clock management

Doc ID 8349 Rev 5

43/166

Figure 19. Using the AVD to monitor VDD

7.6.3

Low power modes

Interrupts

The AVD interrupt event generates an interrupt if the corresponding enable control bit

(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

VDD

VIT+(AVD)

VIT-(AVD)

AVDF bit

RESET

if AVDIE bit = 1

Vhyst

AVD interrupt

request

Interrupt cleared by

VIT+(LVD)

VIT-(LVD)

LVD RESET

Early warning interrupt

(Power has dropped, MCU not

not yet in reset)

hardware

Interrupt cleared by

reset

Table 9.

Effect of low power modes on SI

Mode

Description

WAIT

No effect on SI. AVD interrupts cause the device to exit from WAIT mode.

HALT

The SICSR register is frozen. The AVD remains active.

Table 10.

Interrupt control bits

Interrupt event

Event flag

Enable control bit

Exit from Wait

Exit from Halt

AVD event

AVDF

AVDIE

Yes

ST7LITE25F2 数据表(PDF) 43 Page - STMicroelectronics

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