ST7LITE25F2 datasheet(19/166 Pages) STMICROELECTRONICS

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0037h

ITC

EICR

External Interrupt Control Register

00h

R/W

0038h

MCC

MCCSR

Main Clock Control/Status Register

00h

R/W

0039h

003Ah

Clock and

Reset

RCCR

SICSR

RC oscillator Control Register

System Integrity Control/Status Register

FFh

0000 0XX0h

R/W

003Bh

Reserved area (1 byte)

003Ch

ITC

EISR

External Interrupt Selection Register

0Ch

R/W

003Dh to

0048h

Reserved area (12 bytes)

0049h

004Ah

AWU

AWUPR

AWUCSR

AWU Prescaler Register

AWU Control/Status Register

FFh

00h

R/W

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

DM(4)

DMCR

DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

DM Control Register

DM Status Register

DM Breakpoint Register 1 High

DM Breakpoint Register 1 Low

DM Breakpoint Register 2 High

DM Breakpoint Register 2 Low

00h

R/W

0051h to

007Fh

Reserved area (47 bytes)

Legend: x = undefined, R/W = read/write.

The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the

I/O pins are returned instead of the DR register contents.

The bits associated with unavailable pins must always keep their reset value.

For a description of the Debug Module registers, see ICC reference manual.

Table 3.

Hardware register map(1) (continued)

Address

Block

label

Reset

status

Remarks

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