ST7LITE25F2 datasheet(97/166 Pages) STMICROELECTRONICS

97 / 166 page

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

On-chip peripherals

Doc ID 8349 Rev 5

97/166

Clearing the MODF bit is done through a software sequence:

A read access to the SPICSR register while the MODF bit is set.

A write to the SPICR register.

Note:

To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high

during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their

original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set

except in the MODF bit clearing sequence.

In a slave device, the MODF bit can not be set, but in a multi master configuration the Device

can be in slave mode with the MODF bit set.

The MODF bit indicates that there might have been a multi-master conflict and allows

software to handle this using an interrupt routine and either perform to a reset or return to an

application default state.

Overrun condition (OVR)

An overrun condition occurs, when the master device has sent a data byte and the slave

device has not cleared the SPIF bit issued from the previously transmitted byte.

When an overrun occurs:

–

The OVR bit is set and an interrupt request is generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A

read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

Write collision error (WCOL)

A write collision occurs when the software tries to write to the SPIDR register while a data

transfer is taking place with an external device. When this happens, the transfer continues

uninterrupted; and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also Section : Slave select

management.

Note:

A "read collision" will never occur since the received data byte is placed in a buffer in which

access is always synchronous with the CPU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is

generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 47: Clearing the

WCOL bit (write collision flag) software sequence).

ST7LITE25F2 数据表(PDF) 97 Page - STMicroelectronics

ST7LITE25F2 数据表(HTML) 97 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载