ST7LITE25F2 datasheet(95/166 Pages) STMICROELECTRONICS

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On-chip peripherals

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Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

Slave mode operation

In slave mode, the serial clock is received on the SCK pin from the master device.

To operate the SPI in slave mode:

Write to the SPICSR register to perform the following actions:

–

Select the clock polarity and clock phase by configuring the CPOL and CPHA bits

(see Figure 46: Data clock timing diagram).

Note:

The slave must have the same CPOL and CPHA settings as the master.

–

Manage the SS pin as described in Slave select management and Figure 44:

Generic SS timing diagram. If CPHA=1 SS must be held low continuously. If

CPHA=0 SS must be held low during byte transmission and pulled up between

each byte to let the slave write in the shift register.

Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI

I/O functions.

Slave mode transmit sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift

The transmit sequence begins when the slave device receives the clock signal and the most

significant bit of the data on its MOSI pin.

When data transfer is complete:

–

The SPIF bit is set by hardware.

–

An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR

Clearing the SPIF bit is performed by the following software sequence:

An access to the SPICSR register while the SPIF bit is set.

A write or a read to the SPIDR register.

Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

The SPIF bit can be cleared during a second transmission; however, it must be cleared

before the second SPIF bit in order to prevent an Overrun condition (see Section : Overrun

condition (OVR)).

11.4.4

Clock phase and clock polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA

bits (See Figure 46: Data clock timing diagram).

Note:

The idle state of SCK must correspond to the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data

capture clock edge.

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