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ST7LITE25F2 数据表(PDF) 13 Page - STMicroelectronics |
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ST7LITE25F2 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 166 page ![]() ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Description Doc ID 8349 Rev 5 13/166 Figure 1. General block diagram 8-bit core ALU OSC1 OSC2 RESET Port A Internal clock Control RAM (384 bytes) PA7:0 (8 bits) VSS VDD Power supply Program (8 Kbytes) LVD memory PLL x 8 Ext. 1 MHz PLL Int. 1MHz 8-bit Lite timer 2 Port B SPI PB6:0 (7 bits) Data EEPROM (256 bytes) 1% RC OSC to 16 MHz ADC + Op-amp 12-bit Auto-reload Timer 2 CLKIN / 2 or PLL X4 8 MHz -> 32 MHz Watchdog Debug module |
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