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ST7LITE25F2 数据表(PDF) 34 Page - STMicroelectronics

部件名 ST7LITE25F2
功能描述  8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, Timers, SPI
PDF  166 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7LITE25F2 数据表(HTML) 34 Page - STMicroelectronics

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Doc ID 8349 Rev 5
Note:
See Section 13: Electrical characteristics for more information on the frequency and
accuracy of the RC oscillator.
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7
device.
These two bytes are systematically programmed by ST, including on FASTROM devices.
Consequently, customers intending to use FASTROM service must not use these two bytes.
RCCR0 and RCCR1 calibration values will be erased if the Read-out protection bit is reset
after it has been set. See Section 4.5.1: Read-out protection.
Caution:
If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
7.2
Phase locked loop (PLL)
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external
clock by 4 or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor
of 4 or 8 is selected by 2 option bits.
The x4 PLL is intended for operation with VDD in the 2.4 V to 3.3 V range
The x8 PLL is intended for operation with VDD in the 3.3 V to 5.5 V range
Note:
Refer to Section 15.1: Option bytes for the option byte description.
If the PLL is disabled and the RC oscillator is enabled, then fOSC = 1 MHz.
If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock.
Figure 12. PLL output frequency timing diagram
When the PLL is started, after reset or wakeup from HALT mode or AWUF mode, it outputs
the clock after a delay of tSTARTUP.
When the PLL output signal reaches the operating frequency, the LOCKED bit in the
SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of
4/8 x
freq.
LOCKED bit set
tSTAB
tLOCK
input
tSTARTUP
t



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