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ST7LITE25F2 数据表(PDF) 128 Page - STMicroelectronics |
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ST7LITE25F2 数据表(HTML) 128 Page - STMicroelectronics |
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128 / 166 page  Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 128/166 Doc ID 8349 Rev 5 Figure 65. Typical IDD vs. temperature at VDD = 5V and fCPU = 8MHz 13.5 Clock and timing characteristics Subject to general operating conditions for VDD, fOSC, and TA. Table 68. On-chip peripherals Symbol Parameter Conditions Typ Unit IDD(AT) 12-bit Auto-Reload Timer supply current(1) 1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM mode at fcpu= 8MHz. fCPU=4MHz VDD=3.0V 300 μA fCPU=8MHz VDD=5.0V 1000 IDD(SPI) SPI supply current (2) 2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communication (data sent equal to 55h). fCPU=4MHz VDD=3.0V 50 fCPU=8MHz VDD=5.0V 300 IDD(ADC) ADC supply current when converting (3) 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with amplifier off. fADC=4MHz VDD=3.0V 250 VDD=5.0V 1100 2.0 3.0 4.0 5.0 6.0 7.0 8.0 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 Vdd (V) 25° -45° 90° 130° Table 69. General Timings Symbol Parameter(1) 1. Guaranteed by design. Not tested in production. Conditions Min Typ(2) 2. Data based on typical application software. Max Unit tc(INST) Instruction cycle time fCPU=8MHz 23 12 t CPU 250 375 1500 ns tv(IT) Interrupt reaction time(3) tv(IT) = Δtc(INST) + 10 3. Time measured between interrupt event and interrupt vector fetch. Dtc(INST) is the number of tCPU cycles needed to finish the current instruction execution. fCPU=8MHz 10 − 22 t CPU 1.25 − 2.75 μs |
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