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数据搜索系统，热门电子元器件搜索 |
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STM32F217VG 数据表(PDF) 148 Page - STMicroelectronics |
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STM32F217VG 数据表(HTML) 148 Page - STMicroelectronics |
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148 / 175 page  Electrical characteristics STM32F21xxx 148/175 DocID17050 Rev 9 Figure 73. SD default mode 6.3.28 RTC characteristics Table 84. SD / MMC characteristics Symbol Parameter Conditions Min Max Unit fPP Clock frequency in data transfer mode CL ≤ 30 pF 0 48 MHz - SDIO_CK/fPCLK2 frequency ratio - - 8/3 - tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF 32 ns tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF 31 tr Clock rise time CL ≤ 30 pF 3.5 tf Clock fall time CL ≤ 30 pF 5 CMD, D inputs (referenced to CK) tISU Input setup time CL ≤ 30 pF 2 ns tIH Input hold time CL ≤ 30 pF 0 CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time CL ≤ 30 pF 6 ns tOH Output hold time CL ≤ 30 pF 0.3 CMD, D outputs (referenced to CK) in SD default mode(1) 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. tOVD Output valid default time CL ≤ 30 pF 7 ns tOHD Output hold default time CL ≤ 30 pF 0.5 ai14888 CK D, CMD (output) tOVD tOHD Table 85. RTC characteristics Symbol Parameter Conditions Min Max -fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4- |
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