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AS3953

Datasheet - D e t a il e d D es c r i pt io n

7.6.1 Passing of Block Data to Controller

After the PICC Logic has passed the anti-collision procedure and replied with SAK on Cascade Level 2 it passes in ACTIVE(*) state. On this level

it expects that blocks received from the PCD have the format according to ISO 14443A-4. The ISO 144443A Logic recognizes the command by

observing the first received byte. Based on content of this byte command is either processed by the AS3953 or the complete block data is put in

the FIFO for further processing by the controller. The table below displays the decision criteria.

As shown in Table 3, the block data is put in the FIFO whenever the two MSB bits are 00 or 10 and also in the case when the four MSB bits are

1111. Therefore the implemented communication between the PCD and a tag implemented by the AS3953 and a controller does not need to

follow the Block transmission protocol defined in the ISO 14443-4.

7.6.2 Use of CID

As mentioned above the AS3953 decides depending on content of the first byte of received message to either execute received message as a

command or to put it in the FIFO. The second byte of the message comprises a CID number which is attributed by PCD. PCD will use CID

number in case more PICCs are brought to Level-4 of communication at the same time.

CID is only checked for messages (commands) that are executed by the AS3953. In case CID does not match such a command is rejected (no

action is taken).

Messages that are based on first byte are put in FIFO and are not filtered by CID. It is left to controller to check for the CID and decide whether

or not to reply (CID number is stored in the RATS Register).

7.7 ISO 14443A Level-3 Protocol Mode

Level-3 Protocol mode is intended for implementation of custom protocols for which coding on Level-4 of ISO 14443A communication according

to Table 3 is not appropriate. In this mode Level-2 and Level-3 behavior of the PICC logic is identical to ISO 14443A Level-4 Protocol mode,

while on Level-4 all received data blocks are put in FIFO.

In case the configuration bit

irq_l4 is set an interrupt is automatically sent to controller once the PICC Logic enters in ACTIVE(*) state (after

sending SAK on Cascade Level 2).

In this mode the EEPROM can be accessed via SPI when the RF field is active.

Table 3. First byte of the ISO 14443-4 PCD Block

First Byte

Comment

Action of PICC Logic

1110 0000

RATS

Replies with ATS

1

1.

RATS and PPS are only processed by the AS3953 logic in case they are sent according to the ISO 14443-4 specification (RATS is first

command sent after entry in ACTIVE(*) state, optionally followed by

PPS). In case RATS or PPS are sent once the AS3953 logic is in

PROTOCOL state the information received is saved into FIFO and not acted upon.

1110 not(0000)

Block is put in FIFO

1101 xxxx

PPS

Replies with PPS response (second character is CID)

1

1100 x 010

DESELECT

Replies and go to Halt

1100 x not(010)

(see footnote 2)

Block is put in FIFO

1111 xxxx

WTX, S(PARAMETERS), RFU

2

2. Compatible with old and new S(PARAMETERS) definition: Old: 1100 x000 is S(PARAMETERS) block according to the ISO 14443-4/

AM2. New: 1111 x000 is S(PARAMETERS) block according to the modification SC17/WG8.

Block is put in FIFO since controller needs it to implement chaining

01xx xxxx

Proprietary command

Proprietary command is processed

00xx xxxx

I-block

Block is put in FIFO

10xx xxxx

R-block