www.ams.com

Revision 1.0

28 - 42

AS3953

Datasheet - A pp l ic a t io n I n f or m a t i on

8.1.8 Interrupt Interface

There are two interrupt registers implemented in the AS3953 (Main Interrupt Register and Auxiliary Interrupt Register). Main Interrupt

Register

contains information about seven interrupt sources, while one bit references to interrupt sources detailed in Auxiliary Interrupt

Register

.

When an interrupt condition is met the source of interrupt bit is set in the Main Interrupt Register and the IRQ pin transitions to high.

The controller then reads the Main Interrupt Register to distinguish between different interrupt sources. In case the bit

l_aux is pointing to the

Auxiliary Interrupt Register

, this register also needs to be read. After an interrupt register (main or auxiliary) is read its content is reset to ‘0’.

Exception to this rule is the bit pointing to auxiliary register. This bit is only cleared when the auxiliary interrupt register is read. IRQ pin transitions

to high after the interrupt bit(s) which caused its transition to high has been read. Please note that there may be more than one interrupt register

bit set in case the controller did not immediately read the Interrupt registers after the IRQ signal is set and another event causing interrupt

occurred.

8.1.9 FIFO Water Level and FIFO Status Register

The AS3953 contains a 32 byte FIFO. In case of transmitting the Control logic shifts data which was previously loaded by the external controller

to the Framing Block and further to the Transmitter. During reception, the demodulated data is stored in the FIFO and the external controller can

download received data.

Transmit and receive capability of the AS3953 is not limited by of the FIFO size due to a FIFO water level interrupt system. During transmission

an interrupt is sent (interrupt due to FIFO water level in the Main Interrupt Register) when the content of data in the FIFO which still need to be

sent is lower than the FIFO water level for transmit. The external controller can now add more data in the FIFO. The same stands for receive

mode. In case the number of received bytes increases over the FIFO water level for receive an interrupt is sent to inform the external controller

that data has to be downloaded from FIFO.

The external controller has to serve the FIFO faster than data is transmitted or received. A general rule is that the SCLK frequency has to be at

least double than the actual data rate in receive or transmit.

FIFO water level is set to ¾ of FIFO for reception and to ¼ of FIFO for transmission. This means that in case of getting an interrupt during

reception there are already 24 bytes in the FIFO, which have to be read out to liberate space for following data bytes. Same stands for

transmission, water level interrupt is sent when there are 8 bytes left in FIFO, therefore up to 24 additional bytes can be loaded.

During FIFO operation (FIFO read or FIFO load) the water level detection system is blocked to avoid spurious water level interrupts (these might

occur when for example number of bytes has increased above water level during loading and immediately after that dropped again below water

level due to Tx process which runs in parallel). Due to this the FIFO loading/reading rate has to be higher than Tx / Rx bit rate, once FIFO

loading/reading is finished the /SS pin has to be pulled to VDD (logic remains in FIFO load/read mode as long as /SS remains low).

In case loading/reading of FIFO is not much faster than Tx / Rx processes low the following two cases have to be considered:



FIFO underflow IRQ is not blocked, in case loading in FIFO is slower than transmission process the FIFO underflow IRQ is produced.



In case of slow FIFO loading it is possible that the content of FIFO is increased above water level but it is below when FIFO loading is fin-

ished. In such case a water level IRQ is issued after termination of FIFO loading. Same stands for FIFO reading.



In case of slow FIFO loading it is possible that the content of FIFO stays below water level during complete FIFO loading operation. In such

case water level IRQ is not issued after termination of FIFO loading. Same stands for FIFO reading.

In case it is known that the receive data frame is smaller than the FIFO size the water level interrupt does not have to be served. In such case the

water level interrupt can be masked.

After data is received the external controller needs to know how long the receive data string was before downloading data from the FIFO: This

information is available in the FIFO Status Register 1 and FIFO Status Register 2 which display number of bytes in the FIFO which were not

read out.

The FIFO Status Register 2 additionally contains two bits which indicate that the FIFO was not correctly served during reception or transmission

process (FIFO overflow and FIFO underflow).

FIFO overflow is set when too much data is written in FIFO. In case this bit is set during reception the external controller did not react on time on

water level IRQ and more than 32 bytes were written in the FIFO. The received data is corrupted in such a case. During transmission this means

that controller has written more data than FIFO size. The data to be transmitted is corrupted.

FIFO underflow is set when data was read from empty FIFO. In case this bit is set during reception the external controller read more data than

was actually received. During transmission this means that controller has failed to provide the quantity of data defined in number of transmitted

bytes registers on time.