AS3953_07 datasheet(33/42 Pages) AMSCO

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AS3953

Datasheet - A pp l ic a t io n I n f or m a t i on

8.3.5 Interrupt Register and Associated Registers

Mask Main Interrupt Register.

Note:

Default setting is set at power-up and after

Set Default command.

Mask Auxiliary Interrupt Register.

Note:

Default setting is set at power-up and after

Set Default command.

Address# 08h : Mask Main Interrupt

Type: RW

Bit

Name

Default

Function

Comments

M_pu

Mask power-up IRQ

This bit is set to ‘0’ during power-up

initialization in case EEPROM configuration

bit

irq_pu is set to ‘1’

M_wu_l4

Mask wake-up IRQ at entry in ACTIVE(*)

state

This bit is set to ‘0’ during power-up

initialization in case EEPROM configuration

bit

irq_l4 is set to ‘1’

M_wu

Mask wake-up IRQ triggered by sending

Wake-up command

M_rxs

Mask IRQ due to start of receive

M_rxe

Mask IRQ due to end of receive

M_txe

Mask IRQ due to end of transmission

M_wl

Mask IRQ due to FIFO water level

RFU

Address# 09h : Mask Auxiliary Interrupt

Type: RW

Bit

Name

Default

Function

Comments

M_des

Mask IRQ due to reception of

DESELECT

command

M_er_fr

Mask Framing error IRQ

M_er_par

Mask Parity error IRQ

M_er_crc

Mask CRC error IRQ

M_er_fifo

Mask FIFO error IRQ

M_eew

Mask IRQ due to successful termination of

EEPROM programming

M_er_eew

Mask error during EEPROM programming

IRQ

M_ee_spi

Mask IRQ due to interruption of EEPROM

access due to PICC interface activation

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