AS3953_07 datasheet(31/42 Pages) AMSCO

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AS3953

Datasheet - A pp l ic a t io n I n f or m a t i on

8.3.3 Mode Definition Registers

Mode Definition Register.

Note:

Default value is loaded from EEPROM configuration word bits

b12 to b7 during power-up initialization.

Bit Rate Definition Register.

Note:

Default setting is set at power-up and after

Set Default command. In ISO 14443A Level-4 Protocol mode, this value is rewritten after

receiving

PPS command.

Table below defines the coding of the Bit Rate

Note:

In case a bit rate which is not supported is selected, the Tx / Rx operation is disabled.

Address# 01h : Mode Definition

Type: RW

Bit

Name

Default

Function

Comments

RFU

r_mod_1

see note 00: ISO 14443A Level-4 Protocol mode

01:

ISO 14443A Level-3 Protocol mode

10:

Framing mode

11:

Transparent mode

ISO mode in case of register control;

If ISO 14443A Protocol mode is selected

through registers, logic is forced in Level-4

mode.

r_mod_2

see note

r_rxncrc

see note

Rx – CRC is not checked, CRC part of

message is also put in FIFO

Applicable in ISO 14443A Level-3 Protocol

mode and Framing mode. In Protocol mode,

applicable for frames which are put in FIFO.

r_rxbs

see note

Rx – Bit stream mode, received bits are

put in FIFO (no parity and CRC check)

r_txncrc

see note 1: Tx – Do not generate CRC

r_txbs

see note

Tx – Bit stream mode, bits put in FIFO

are sent without parity and CRC generation

Address# 02h : Bit Rate Definition

Type: RW

Bit

Name

Default

Function

Comments

tx_rate3

Bit rate for Tx

For coding see table below

tx_rate2

tx_rate1

tx_rate0

rx_rate3

Bit rate for Rx

For coding see table below

rx_rate2

rx_rate1

rx_rate0

Rate3

Rate2

Rate1

Rate0

Bit Rate [kbps]

Comments

fc/128 (~106)

fc/64 (~212)

fc/32 (~424)

fc/16 (~848)

Other combinations RFU

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