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AS3953

Datasheet - A pp l ic a t io n I n f or m a t i on

Main Interrupt Register.

Notes:

1. At power-up and after

Set Default command, content of this register is set to ‘0’.

2. After Main Interrupt Register is read, with the exception of bit0, the register content is set to ‘0’. The bit0 is set to ‘0’ only after the

corresponding interrupt register is read.

Auxiliary Interrupt Register.

Notes:

1. At power-up and after

Set Default command content of this register is set to 0.

2. After Auxiliary Interrupt Register has been read its content is set to 0.

Address# 0Ah : Main Interrupt

Type: R

Bit

Name

Function

Comments

7

I_pu

Power-up IRQ

6

I_wu_l4

Wake-up IRQ at entry in ACTIVE(*) state

5

I_wu

Wake-up IRQ triggered by sending

Wake-up

command

4

I_rxs

IRQ due to start of receive

Applicable when receive frame is put in FIFO

3

I_rxe

IRQ due to end of receive

Applicable when receive frame is put in FIFO

2

I_txe

IRQ due to end of transmission

Applicable when data from FIFO is sent

1

I_wl

IRQ due to FIFO water level

During receive informing that FIFO is almost

full and has to be read out.

During transmit informing that FIFO is almost

empty and that additional data has to be send

0

I_aux

IRQ due to event displayed in the Auxiliary

Interrupt Register

Address# 0Bh : Auxiliary Interrupt

Type: R

Bit

Name

Function

Comments

7

I_des

IRQ due to reception of

DESELECT command

6

I_er_fr

Framing error

5

I_er_par

Parity error

In case of parity or/and CRC error the receive

data is still put in FIFO, error IRQ is

additionally send.

4

I_er_crc

CRC error

3

I_er_fifo

FIFO error (overflow/underflow)

See FIFO Status Register 2

2

I_eew

IRQ due to successful termination of EEPROM

programming

In case EEPROM write command was sent

through SPI

1

I_er_eew

Error during EEPROM programming (writing to write

protected word, writing to nonexistent address)

In case EEPROM write command was sent

through SPI

0

I_ee_spi

IRQ due to interruption of EEPROM access due to

PICC interface activation