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AS3953

Datasheet - A pp l ic a t io n I n f or m a t i on

8.1.10 ISO 14443A Frame Data in FIFO

Data in ISO 14443A frames is organized in bytes; each byte is terminated by parity bit. Data bits in a byte are numbered from

b1 to b8 where b1

is LSB bit, LSB is sent first.

Data sent over SPI is also organized in bytes, bits in a byte are marked

D0 to D7, where D0 is LSB bit, MSB is sent first.

During receive the framing engine checks the parity bit and removes it from data frame, only the data bytes are put in FIFO. During transmission

the process is inversed, only the data bytes are put in FIFO, while the framing engine adds the parity bits.

The ISO 14443A data bits

b1 to b8 are mapped to FIFO data bits D0 to D7, which means that the order of receiving/transmitting bits in a byte is

inversed (the ISO 14443A bytes are sent LSB first while the SPI bytes are sent MSB first).

The only exceptions to this rule are the Rx and Tx bit stream modes. In these modes the meaning of byte is lost. In order to simplify processing

the order of bits is the same on ISO 14443A and FIFO side.

This means that during reception with bit

rxbs set the first received bit is also the first bit read out of FIFO. In case the last FIFO byte is not

complete the bits which are not part of received data are padded with ‘0’.

The same stands for transmission with bit

txbs set: the first bit written in FIFO is also the first bit sent.

8.2 Direct Commands

8.2.1 Set Default

This direct command puts the AS3953 in the same state as power-up initialization. All registers are initialized to the default state.

8.2.2 Clear

This direct command stops all current activities (transmission or reception) and clears FIFO.

8.2.3 Transmit

This direct command transmits the data stored in the FIFO. In Protocol modes it is only accepted on Level-4 of communication. Before triggering

transmission using

Transmit command direct command Clear has to be sent, followed by definition of number of transmitted bytes and writing

data to be transmitted in FIFO.

Execution of this direct command is only enabled when the AS3953 antenna coil is in a PCD field (VP_INT is above HF_PON threshold).

8.2.4 Go2halt

Puts PICC logic in HALT state.

Execution of this direct command is only enabled when the AS3953 antenna coil is in a PCD field (VP_INT is above HF_PON threshold) and

PICC Logic is in one of the two ISO 14443A Protocol modes.

Table 10. List of Direct commands

Command Byte Value

[hex]

Command

Comments

C2, C3

Set Default

Puts the AS3953 in default state

C4, C5

Clear

Stops all activities and clears FIFO

C8

Transmit

Starts a transmit sequence

D0

Go2halt

Puts PICC logic in HALT state