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MPC5601PEF0MLL4R 数据表(PDF) 45 Page - Freescale Semiconductor, Inc |
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MPC5601PEF0MLL4R 数据表(HTML) 45 Page - Freescale Semiconductor, Inc |
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45 / 95 page ![]() MPC5602P Microcontroller Data Sheet, Rev. 4.1 Freescale Semiconductor 45 • Several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage regulator, I/Os, flash memory and low voltage domain). LVDs are gated low when POWER_ON is active. • A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active high and released to all modules including I/Os, flash memory and 16 MHz RC oscillator needed during power-up phase and reset phase. When POWER_OK is low the associated modules are set into a safe state. Figure 9. Power-up typical sequence VDD_HV_REG 0V 3.3V 0V 3.3V VDD_LV_REGCOR 0V 1.2V 0V 3.3V POWER_ON LVDM (HV) 0V LVDD (LV) 3.3V 0V POWER_OK 3.3V RC16MHz Oscillator 0V 1.2V P0 P1 0V 1.2V Internal Reset Generation Module FSM ~1us VPOR_UP VPORH VLVDHV3H VMLVDOK_H |
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