MPC5601PEF0MLL4R datasheet(1/95 Pages) FREESCALE

部件名	MPC5601PEF0MLL4R

功能描述	MPC5602P Microcontroller Data Sheet

PDF	95 Pages

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制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5602P

Rev. 4.1, 09/2011

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

MPC5602P

64 LQFP (10 mm x 10 mm)

100 LQFP (14 mm x 14 mm)

MPC5602P Microcontroller

Data Sheet

• Up to 64 MHz, single issue, 32-bit CPU core complex

(e200z0h)

– Compliant with Power Architecture embedded category

– Variable Length Encoding (VLE)

• Memory organization

– Up to 256 KB on-chip code flash memory with ECC and

erase/program controller

– Optional: additional 64 (4 × 16) KB on-chip data flash

memory with ECC for EEPROM emulation

– Up to 20 KB on-chip SRAM with ECC

• Fail-safe protection

– Programmable watchdog timer

– Non-maskable interrupt

– Fault collection unit

• Nexus L1 interface

• Interrupts and events

– 16-channel eDMA controller

– 16 priority level controller

– Up to 25 external interrupts

– PIT implements four 32-bit timers

– 120 interrupts are routed via INTC

• General purpose I/Os

– Individually programmable as input, output or special

function

– 37 on 64 LQFP

– 64 on 100 LQFP

• 1 general purpose eTimer unit

– 6 timers each with up/down capabilities

– 16-bit resolution, cascadeable counters

– Quadrature decode with rotation direction flag

– Double buffer input capture and output compare

• Communications interfaces

– Up to 2 LINFlex modules (1× Master/Slave, 1× Master

only)

– Up to 3 DSPI channels with automatic chip select

generation (up to 8/4/4 chip selects)

– 1 FlexCAN interface (2.0B Active) with 32 message

buffers

– 1 safety port based on FlexCAN with 32 message

buffers and up to 8 Mbit/s at 64 MHz capability usable

as second CAN when not used as safety port

• One 10-bit analog-to-digital converter (ADC)

– Up to 16 input channels (16 ch on 100 LQFP and 12 ch

on 64 LQFP)

– Conversion time < 1 µs including sampling time at full

precision

– Programmable Cross Triggering Unit (CTU)

– 4 analog watchdogs with interrupt capability

• On-chip CAN/UART bootstrap loader with Boot Assist

Module (BAM)

• 1 FlexPWM unit

– 8 complementary or independent outputs with ADC

synchronization signals

– Polarity control, reload unit

– Integrated configurable dead time unit and inverter fault

input pins

– 16-bit resolution

– Lockable configuration

• Clock generation

– 4–40 MHz main oscillator

– 16 MHz internal RC oscillator

– Software-controlled FMPLL capable of up to 64 MHz

• Voltage supply

– 3.3 V or 5 V supply for I/Os and ADC

– On-chip single supply voltage regulator with external

ballast transistor

• Operating temperature ranges: –40 to 125 °C or –40 to

105 °C

类似零件编号 - MPC5601PEF0MLL4R

制造商	部件名	数据表	功能描述
NXP Semiconductors	MPC5601PEF0MLL4R	2Mb / 95P	MPC5602P Microcontroller Data Sheet Rev. 6,12/2012

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