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MPC5601PEF0MLL4R 数据表(PDF) 16 Page - Freescale Semiconductor, Inc |
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MPC5601PEF0MLL4R 数据表(HTML) 16 Page - Freescale Semiconductor, Inc |
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16 / 95 page ![]() MPC5602P Microcontroller Data Sheet, Rev. 4.1 Freescale Semiconductor 16 • Clock frequency same as that used for e200z0h core • PWM outputs can operate as complementary pairs or independent channels • Can accept signed numbers for PWM generation • Independent control of both edges of each PWM output • Synchronization to external hardware or other PWM supported • Double buffered PWM registers — Integral reload rates from 1 to 16 — Half cycle reload capability • Multiple ADC trigger events can be generated per PWM cycle via hardware • Write protection for critical registers • Fault inputs can be assigned to control multiple PWM outputs • Programmable filters for fault inputs • Independently programmable PWM output polarity • Independent top and bottom deadtime insertion • Each complementary pair can operate with its own PWM frequency and deadtime values • Individual software-control for each PWM output • All outputs can be programmed to change simultaneously via a “Force Out” event • PWMX pin can optionally output a third PWM signal from each submodule • Channels not used for PWM generation can be used for buffered output compare functions • Channels not used for PWM generation can be used for input capture functions • Enhanced dual-edge capture functionality • eDMA support with automatic reload • 2 fault inputs • Capture capability for PWMA, PWMB, and PWMX channels not supported 1.5.25 eTimer The MPC5602P includes one eTimer module which provides six 16-bit general purpose up/down timer/counter units with the following features: • Clock frequency same as that used for the e200z0h core • Individual channel capability — Input capture trigger — Output compare — Double buffer (to capture rising edge and falling edge) — Separate prescaler for each counter — Selectable clock source — 0–100% pulse measurement — Rotation direction flag (quad decoder mode) • Maximum count rate — External event counting: max. count rate = peripheral clock/2 — Internal clock counting: max. count rate = peripheral clock • Counters are: — Cascadable — Preloadable • Programmable count modulo • Quadrature decode capabilities |
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