MPC5601PEF0MLL4R datasheet(18/95 Pages) FREESCALE

18 / 95 page

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

•

Trigger generation unit configurable in sequential mode or in triggered mode

•

Each trigger can be appropriately delayed to compensate the delay of external low pass filter

•

Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation

•

Double buffered ADC command list pointers to minimize ADC-trigger unit update

•

Double buffered ADC conversion command list with up to 24 ADC commands

•

Each trigger capable of generating consecutive commands

•

ADC conversion command allows to control ADC channel, single or synchronous sampling, independent result queue

selection

1.5.28

Nexus Development Interface (NDI)

The NDI (Nexus Development Interface) block provides real-time development support capabilities for the MPC5602P Power

Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for

MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several

individual Nexus blocks that are selected to provide the development support interface for this device. The NDI block interfaces

to the host processor and internal busses to provide development support as per the IEEE-ISTO 5001-2003 Class 2+ standard.

The development support provided includes access to the MCU’s internal memory map and access to the processor’s internal

registers during run time.

The NDI provides the following features:

•

Configured via the IEEE 1149.1

•

All Nexus port pins operate at VDDIO (no dedicated power supply)

•

Nexus 2+ features supported

— Static debug

— Watchpoint messaging

— Ownership trace messaging

— Program trace messaging

— Real time read/write of any internally memory mapped resources through JTAG pins

— Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow overwrite of

information

— Watchpoint triggering, watchpoint triggers program tracing

•

Auxiliary Output Port

— 4 MDO (Message Data Out) pins

— MCKO (Message Clock Out) pin

—2 MSEO (Message Start/End Out) pins

—EVTO (Event Out) pin

•

Auxiliary Input Port

—EVTI (Event In) pin

1.5.29

Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:

•

Support for CRC-16-CCITT (x25 protocol):

— x16 + x12 + x5 + 1

•

Support for CRC-32 (Ethernet protocol):

— x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

•

Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency

MPC5601PEF0MLL4R 数据表(PDF) 18 Page - Freescale Semiconductor, Inc

MPC5601PEF0MLL4R 数据表(HTML) 18 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

数据表下载