MPC5601PEF0MLL4R datasheet(17/95 Pages) FREESCALE

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MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

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Counters can share available input pins

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Count once or repeatedly

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Pins available as GPIO when timer functionality not in use

1.5.26

Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

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1 on-chip analog-to-digital converter

— 10-bit AD resolution

— 1 sample and hold unit

— Conversion time, including sampling time, less than 1 µs (at full precision)

— Typical sampling time is 150 ns minimum (at full precision)

— DNL/INL ±1 LSB

—TUE < 1.5 LSB

— Single-ended input signal up to 3.3 V/5.0 V

— 3.3 V/5.0 V input reference voltage

— ADC and its reference can be supplied with a voltage independent from VDDIO

— ADC supply can be equal or higher than VDDIO

— ADC supply and ADC reference are not independent from each other (both internally bonded to same pad)

— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

Digital part:

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16 input channels

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4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in

the appropriate ADC result location

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2 modes of operation: Motor Control mode or Regular mode

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Regular mode features

— Register based interface with the CPU: control register, status register and 1 result register per channel

— ADC state machine managing 3 request flows: regular command, hardware injected command and software

injected command

— Selectable priority between software and hardware injected commands

— DMA compatible interface

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CTU-controlled mode features

— Triggered mode only

— 4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)

— Result alignment circuitry (left justified and right justified)

— 32-bit read mode allows to have channel ID on one of the 16-bit part

— DMA compatible interfaces

1.5.27

Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU

load during the PWM period and with minimized CPU load for dynamic configuration.

It implements the following features:

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Double buffered trigger generation unit with up to 8 independent triggers generated from external triggers

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