ADS7253IPW datasheet(30/71 Pages) TI1

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a) ADC_A

b) ADC_B

AINP_B

AVDD

GND

CSAMPLE

AINM_B

AVDD

GND

CSAMPLE

AINP_A

AVDD

GND

CSAMPLE

AINM_A

AVDD

GND

CSAMPLE

ADS8353, ADS7853, ADS7253

SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014

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Feature Description (continued)

8.3.2 Analog Inputs

The ADS8353, ADS7853, and ADS7253 support single-ended or pseudo-differential analog inputs on both ADC

channels. These inputs are sampled and converted simultaneously by the two ADCs, ADC_A and ADC_B.

ADC_A samples and converts (VAINP_A – VAINM_A), and ADC_B samples and converts (VAINP_B – VAINM_B).

Figure 85a and Figure 85b show equivalent circuits for the ADC_A and ADC_B analog input pins, respectively.

Series resistance, RS, represents the on-state sampling switch resistance (typically 50 Ω) and CSAMPLE is the

device sampling capacitor (typically 40 pF).

Figure 85. Equivalent Circuit for the Analog Input Pins

8.3.2.1 Analog Input: Full-Scale Range Selection

The full-scale range (FSR) supported at the analog inputs of the device is programmable with bit B9 of the

configuration register (CFR.B9). This bit is common for both ADCs (ADC_A and ADC_B). The FSR is given by

Equation 1 and Equation 2 :

For CFR.B9 = 0, FSR_ADC_A = 0 to VREF_A and FSR_ADC_B = 0 to VREF_B

(1)

For CFR.B9 = 1, FSR_ADC_A = 0 to 2 × VREF_A and FSR_ADC_B = 0 to 2 × VREF_B

where:

•

VREF_A and VREF_B are the reference voltages going to ADC_A and ADC_B, respectively (as described in the

Reference section).

(2)

Therefore, with appropriate settings of the REFDAC_A and REFDAC_B registers, CFR.B7, and CFR.B9, the

maximum dynamic range of the ADC can be used.

Note that while using CFR.B9 set to 1, care must be taken so that the ADC analog supply (AVDD) is as in

Equation 3 and Equation 4:

2 × VREF_A ≤ AVDD ≤ AVDD(max)

(3)

2 × VREF_B ≤ AVDD ≤ AVDD(max)

(4)

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Product Folder Links: ADS8353 ADS7853 ADS7253

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