ADS7253IPW datasheet(56/71 Pages) TI1

56 / 71 page

ADS8353, ADS7853, ADS7253

SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014

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9.2.2.1 Design Requirements

To design an application circuit optimized to achieve target specifications listed in Table 21.

Table 21. Target Specifications

TARGET SPECIFICATIONS

TEST CONDITIONS

INPUT SIGNAL

SNR

THD

DEVICE

THROUGHPUT

INTERFACE MODE

FREQUENCY

> 83 dB

< -95 dB

ADS8353

100 kHz

Maximum supported

32-CLK, dual-SDO

> 78.5 dB

< –88 dB

ADS7853

100 kHz

Maximum supported

32-CLK, dual-SDO

> 77.5 dB

< –85 dB

ADS7853

100 kHz

Maximum supported

16-CLK, dual-SDO

> 71.5 dB

< –85 dB

ADS7253

100 kHz

Maximum supported

32-CLK, dual-SDO

> 71 dB

< –84 dB

ADS7253

100 kHz

Maximum supported

16-CLK, dual-SDO

9.2.2.2 Detailed Design Procedure

Best practice is for the distortion from the input driver to be at least 10 dB less than the ADC distortion. The

distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting

gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates

the requirement of rail-to-rail swing at the amplifier input. The low-power OPA836, used as an input driver,

provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications.

In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low

without adding distortion to the input signal. To take full advantage of the pseudo-differential input structure of the

ADC, the AINM pin must be driven to the appropriate VDC with the same amplifier and matching source

impedance.

The application circuit illustrated in Figure 109 is optimized to achieve the lowest distortion and lowest noise for a

100-kHz input signal fed to the ADS8353 or ADS7853 or ADS7253 operating at full throughput. The THS4032,

used as an input driver, provides exceptional ac performance because of its extremely low-distortion, low-noise,

and high-bandwidth specifications. In addition, the components of the antialiasing filter are such that the noise

from the front-end circuit is kept low without adding distortion to the input signal. External clamp circuit may be

required to ensure that the inputs to the device do not exceed AVDD.

Figure 103 illustrates the reference driver circuit when operation with an external reference is desired. The

reference voltage is generated by the high-precision, low-noise REF50xx circuit. The output broadband noise of

the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz. The decoupling

capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise, and fast settling

time makes the OPA2350 a good choice for driving this high capacitive load.

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