ADS7253IPW datasheet(52/71 Pages) TI1

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REF5025,

REF5040,

REF5050

(1)

AVDD

OPA2350

0.1

10 µF

1 k

1 µF

ADC_A

REFIN-A

VOUT

0.22

TRIM

10 µF

1 µF

1 k

1 µF

ADC_B

REFIN-B

0.1

10 µF

REFGND-A

REFGND-B

Device

AVDD

ADS8353, ADS7853, ADS7253

SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014

www.ti.com

Typical Applications (continued)

(1) When using the REF5050, AVDD must be set to 5.5 V.

Figure 103. Reference Drive Circuit

9.2.1.1 Design Requirements

To design an application circuit optimized to achieve target specifications listed in Table 20.

Table 20. Target Specifications

TARGET SPECIFICATIONS

TEST CONDITIONS

INPUT SIGNAL

SNR

THD

DEVICE

THROUGHPUT

INTERFACE MODE

FREQUENCY

> 83 dB

< -100 dB

ADS8353

10 kHz

Maximum supported

32-CLK, dual-SDO

> 81 dB

< –95 dB

ADS7853

10 kHz

Maximum supported

32-CLK, dual-SDO

> 77.5 dB

< –85 dB

ADS7853

10 kHz

Maximum supported

16-CLK, dual-SDO

> 71.5 dB

< –88 dB

ADS7253

10 kHz

Maximum supported

32-CLK, dual-SDO

> 70.5 dB

< –80 dB

ADS7253

10 kHz

Maximum supported

16-CLK, dual-SDO

9.2.1.2 Detailed Design Procedure

Best practice is for the distortion from the input driver to be at least 10 dB less than the ADC distortion. The

distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting

gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates

the requirement of rail-to-rail swing at the amplifier input. The low-power OPA836, used as an input driver,

provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications.

In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low

without adding distortion to the input signal.

The application circuit illustrated in Figure 101 is optimized to achieve the lowest distortion and lowest noise for a

10-kHz input signal fed to the ADS8353 or ADS7853 or ADS7253 operating at full throughput with the default 32-

CLK, dual-SDO interface mode. The input signal is processed through a high-bandwidth, low-distortion amplifier

in an inverting gain configuration and a low-pass RC filter before being fed into the device.

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Product Folder Links: ADS8353 ADS7853 ADS7253

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