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ADS7253IPW 数据表(PDF) 53 Page - Texas Instruments |
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ADS7253IPW 数据表(HTML) 53 Page - Texas Instruments |
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53 / 71 page ![]() ±150 ±120 ±90 ±60 ±30 0 0 100 200 300 400 500 Input Frequency (kHz) C001 ±150 ±120 ±90 ±60 ±30 0 0 100 200 300 400 500 Input Frequency (kHz) C003 ±200 ±180 ±160 ±140 ±120 ±100 ±80 ±60 ±40 ±20 0 0 60 120 180 240 300 Input Frequency (kHz) C301 ADS8353, ADS7853, ADS7253 www.ti.com SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014 The ADS7853 and the ADS7253 also support 16-CLK interface modes that achieve the rated throughput rate at much lower SCLK frequencies. However, when using the 16-CLK interface modes, the device receives less acquisition time when compared to the 32-CLK interface modes. The application circuit illustrated in Figure 102 is optimized to achieve the lowest distortion and lowest noise for a 10-kHz input signal fed to the ADS7853 or ADS7253 operating at full throughput with the 16-CLK, dual-SDO interface mode. The input signal is processed through a high-bandwidth, low-distortion amplifier in an inverting gain configuration and a low-pass RC filter before being fed into the device. Figure 103 illustrates the reference driver circuit when operation with an external reference is desired. The reference voltage is generated by the high-precision, low-noise REF50xx circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz. The decoupling capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise, and fast settling time makes the OPA2350 a good choice for driving this high capacitive load. 9.2.1.3 Application Curves To minimize external components and to maximize the dynamic range of the ADC, device is configured to operate with internal reference (CFR.B6 = 1) and 2 x VREF_x input full scale range (CFR.B9 = 1). Figure 104, Figure 105, and Figure 106, show the FFT plots and test results obtained with the ADS8353, ADS7853, and ADS7253, respectively, operating at full throughput with a 32-CLK interface and the circuit configuration of Figure 101. SNR = 83.5 dB THD = –101.2 dB fIN = 10.1 kHz SNR = 82.1 dB THD = –98.2 dB fIN = 10.1 kHz Figure 104. ADS8353 in 32-CLK Interface Mode Figure 105. ADS7853 in 32-CLK Interface Mode SNR = 72.5 dB THD = –94.2 dB fIN = 10.1 kHz Figure 106. ADS7253 in 32-CLK Interface Mode Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 53 Product Folder Links: ADS8353 ADS7853 ADS7253 |
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