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ADS7253IPW 数据表(PDF) 45 Page - Texas Instruments |
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ADS7253IPW 数据表(HTML) 45 Page - Texas Instruments |
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45 / 71 page ![]() 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK CS SDO-A and SDO-B CFG.B[15:12] = 1000b CFG.B[11:6] CFG.B[5] = 1 CFG.B[4:0] = 00000b SDI 1 2 Valid Data as per device configuration N Device enters STANDBY mode Device in STANDBY mode Frame (F) Frame (F+1) ADS8353, ADS7853, ADS7253 www.ti.com SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014 In this mode, at least 32 SCLK falling edges must be given to validate the read/write frame. A CS rising edge ends the frame and puts the serial bus into 3-state. Refer to Table 19 for timing specifications specific to this serial interface mode. Table 19. 16-CLK, Single-SDO Interface Specific Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMING REQUIREMENTS ADS7853 55.5 ns tCLK CLOCK period ADS7253 55.5 ns ADS7853 19 × tCLK ns tACQ Acquisition time ADS7253 21 × tCLK ns TIMING SPECIFICATIONS ADS7853 14 × tCLK ns tCONV Conversion time ADS7253 12 × tCLK ns 8.5.4 Low-Power Modes In normal mode of operation, all internal circuits of the device are always powered up and the device is always ready to commence a new conversion. This mode enables the device to support the rated throughput. The device also supports two low-power modes to optimize the power consumption at lower throughputs: STANDBY mode and software power-down (SPD) mode. 8.5.4.1 STANDBY Mode The device supports a STANDBY mode of operation where some of the internal circuits of the device are powered down. However, if bit 6 in configuration register is set to 1 (CFR.B6 = 1), then the internal reference is not powered down and the contents of the REFDAC_A and REFDAC_B registers are retained to enable faster power-up to a normal mode of operation. As shown in Figure 95, a valid write operation in frame (F) to program the configuration register with B5 set to 1 (CFR.B5 = 1) places the device into a STANDBY mode of operation on the following CS rising edge. While in STANDBY mode, SDO_A and SDO_B output all 1s when CS is low and remain in 3-state when CS is high. To remain in STANDBY mode, SDI must remain low in the subsequent frames. Note that N is a function of the device configuration, as described in Table 4. Figure 95. Enter STANDBY Mode Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 45 Product Folder Links: ADS8353 ADS7853 ADS7253 |
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