ADS7253IPW datasheet(46/71 Pages) TI1

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SCLK

SDO-A

and

SDO-B

CFG.B[15:12] = 1000b

CFG.B[11:6]

CFG.B[5] = 0

CFG.B[4:0] = 00000b

SDI

tPU_STDBY

Valid Data as per device configuration

CFG settings for Frame (F+5)

Frame (F+2)

Device in

STANDBY

mode

Frame (F+3)

Frame (F+4)

Device exits

STANDBY mode

These bits set device

configuration for Frame (F+4)

ADS8353, ADS7853, ADS7253

SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014

www.ti.com

As shown in Figure 96, a valid write operation in frame (F+3) by writing the configuration register with B5 set to 0

(CFR.B5 = 0) brings the device out of STANDBY mode on the following CS rising edge. Frame (F+3) must have

at least 48 SCLK falling edges.

After exiting the STANDBY mode, a delay of tPU_STDBY must elapse for the internal circuits to fully power-up and

resume normal operation in frame (F+4). Device configuration for frame (F+4) is determined by the status of the

CFR.B[11:6] bits programmed during frame (F+3).

Note that N is a function of the device configuration, as described in Table 4.

Figure 96. Exit STANDBY Mode

Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.

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Product Folder Links: ADS8353 ADS7853 ADS7253

ADS7253IPW 数据表(PDF) 46 Page - Texas Instruments

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