ADS7253IPW datasheet(48/71 Pages) TI1

48 / 71 page

SCLK

SDO

tPH_CS_SHRT

tPL_CS

SCLK

SDO

Sample

N + 1

tACQ

Data From Sample N

tPH_CS_SHRT

tCONV

ADS8353, ADS7853, ADS7253

SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014

www.ti.com

8.5.5 Frame Abort, Reconversion, or Short-Cycling

As discussed in Figure 99, the minimum number of SCLK falling edges (N) that must be provided between the

beginning and end of the frame depends on the serial interface mode. The SCLK falling edges (N) program the

device and retrieve the conversion result. If CS is brought high before the expected number of SCLK falling

edges are provided, the current frame is aborted and the device starts sampling the new analog input signal.

If frame (F) is aborted, then the register write operation attempted in frame (F) is considered invalid and the

internal registers are not updated. The device continues to have the same configuration in frame (F+1) from

frame (F).

The output data bits latched before the CS rising edge are still valid data that correspond to sample N.

Figure 99. Frame Abort, Reconversion, or Short-Cycling Feature

Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.

Submit Documentation Feedback

Product Folder Links: ADS8353 ADS7853 ADS7253

ADS7253IPW 数据表(PDF) 48 Page - Texas Instruments