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ADS7253IPW 数据表(PDF) 38 Page - Texas Instruments

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部件名 ADS7253IPW
功能描述  Simultaneous-Sampling, Analog-to-Digital Converters
PDF  71 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ADS7253IPW 数据表(HTML) 38 Page - Texas Instruments

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1
2
N
SCLK
CS
SDO-A
SDI
Valid Data
SDO-B
Valid Data
No change in device
configuration
1
2
16
48
Valid data as per device configuration.
Valid data as per device configuration.
3
4
5
B15
B14 B13
B12
X
X
X
X
1
2
15
16
47
48
R15 R14
R1
R0
1
2
N
Valid Data
Frame (F)
Frame (F+1)
Frame (F+2)
Frame (F+3)
Device configuration for frame (F+3)
Valid Data
No change in device
configuration
ADS8353, ADS7853, ADS7253
SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
www.ti.com
8.5.3 Data Read Operation
The device supports two types of read operations: reading user-programmable registers and reading conversion
results.
8.5.3.1 Reading User-Programmable Registers
The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B.
Figure 90 shows a detailed timing diagram for this operation.
Note that N is a function of the device configuration, as described in Table 4.
Figure 90. Register Readback Timing
To readback the user-programmable register settings, the appropriate control word should be transmitted to the
device during frame (F+1), as shown in Table 9. Frame (F+1) must have at least 48 SCLK falling edges.
Table 9. Control Word to Readback User-Programmable Registers
CONTROL WORD TO BE PROGRAMMED IN FRAME (F+1)
USER-PROGRAMMABLE REGISTER
B[15:12] (Binary)
B[11:0] (Hex)
CFR
0011b
000h
REFDAC_A
0001b
000h
REFDAC_B
0010b
000h
Frame (F+2) must have at least 48 SCLK falling edges. During frame (F+2), SDO_A outputs the contents of the
selected user-programmable register on the first 16 SCLK falling edges (as shown in Table 10) and then outputs
0s for any subsequent SCLK falling edges. The SDO_B pin outputs 0s for all the SCLK falling edges.
Table 10. Register Data Read Back
USER-
DATA READ ON SDO-A IN FRAME (F+2)
PROGRAMMABLE
R15
R14
R13
R12
R11
—
R3
R2
R1
R0
REGISTER
CFR
0
0
1
1
CFG.B11
—
CFG.B3
CFG.B2
CFG.B1
CFG.B0
REFDAC_A
0
0
0
1
REFDAC_A.D8
—
REFDAC_A.D0
0
0
0
REFDAC_B
0
0
1
0
REFDAC_B.D8
—
REFDAC_B.D0
0
0
0
Register settings programmed during frame (F+2) determine the device configuration in frame (F+3).
38
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Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: ADS8353 ADS7853 ADS7253



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