ADS7253IPW datasheet(35/71 Pages) TI1

35 / 71 page

ADS8353, ADS7853, ADS7253

www.ti.com

SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014

8.4 Device Functional Modes

The device provides three user-programmable registers: the configuration register (CFR), the REFDAC_A

Registers section) and readback (refer to the Reading User-Programmable Registers section) operations and

allow the user to customize ADC behavior for specific application requirements.

The device supports four interface modes (refer to the Conversion Data Read section), two low-power modes

(refer to the Low-Power Modes section), and short-cycling/reconversion feature (refer to the Frame Abort,

Reconversion, or Short-Cycling section).

8.5 Register Maps and Serial Interface

8.5.1 Serial Interface

The device uses the serial clock (SCLK) for synchronizing data transfers in and out of the device.

The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends

with a CS rising edge. Between the start and end of the frame, a minimum of N SCLK falling edges must be

provided to validate the read or write operation. As shown in Table 4, N depends upon the interface mode used

to read the conversion result. When N SCLK falling edges are provided, the write operation attempted in the

frame is validated and the internal user-programmable registers are updated on the subsequent CS rising edge.

This CS rising edge also ends the frame.

Table 4. SCLK Falling Edges for a Valid Write Operation

MINIMUM SCLK FALLING EDGES REQUIRED TO

INTERFACE MODE

VALIDATE WRITE OPERATION N

32-CLK, dual-SDO mode (default). See the 32-CLK, Dual-SDO Mode section.

32-CLK, single-SDO mode. See the 32-CLK, Single-SDO Mode section.

16-CLK, dual-SDO mode. See the 16-CLK, Dual-SDO Mode section.

16-CLK, single SDO mode. See the 16-CLK, Single SDO Mode section.

If CS is brought high before providing N SCLK falling edges, the write operation attempted in the frame is not

valid. Refer to the Frame Abort, Reconversion, or Short-Cycling section for more details.

8.5.2 Write to User Programmable Registers

The device features three user-programmable registers: the configuration register (CFR), the REFDAC_A

data on SDI are latched into the device on the first 16 SCLK falling edges. However, the new configuration takes

effect only when the read or write operation is validated. If these registers are not required to update, SDI must

remain low during the respective frames.

The first four SDI data bits (B[15:12]) determine what operation is performed (that is, either a read or write

operation or no operation), which register address the operation uses, and the function of the next 12 SDI data

bits (B[11:0]). Table 5 lists the various combinations supported for B[15:12].

Table 5. Data Write Operation

B15

B14

B13

B12

OPERATION

FUNCTION OF BITS B[11:0]

No operation is performed

These bits are ignored

REFDAC_A read

000h; see the Reading User-Programmable Registers section

REFDAC_B read

000h; see the Reading User-Programmable Registers section

CFR read

000h; see the Reading User-Programmable Registers section

CFR write

See the Configuration Register (CFR) section

REFDAC_A write

See the REFDAC_A section

REFDAC_B write

See the REFDAC_B section

No operation is performed

These bits are ignored

No operation is performed

These bits are ignored

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