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ADS7253IPW 数据表(PDF) 42 Page - Texas Instruments

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部件名 ADS7253IPW
功能描述  Simultaneous-Sampling, Analog-to-Digital Converters
PDF  71 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ADS7253IPW 数据表(HTML) 42 Page - Texas Instruments

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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CS
0
0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
ADS7853, ADS7854
SDO_A and SDO_B
Sample
N
Sample
N + 1
tACQ
tCONV
tTHROUGHPUT
D3
D2
D1
D0
tPH_CS
ADS7253, ADS7254
SDO_A and SDO_B
Data From Sample N
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
SDI
B3
B2
B1
B0
tSCLK
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
tCONV
tACQ
ADS8353, ADS7853, ADS7253
SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
www.ti.com
Refer to Table 15 for timing specifications specific to this serial interface mode.
Table 15. 32-CLK, Single-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
ADS8353
50
ns
tCLK
CLOCK period
ADS7853
29.4
ns
ADS7253
29.4
ns
tACQ
Acquisition time
49 × tCLK – tCONV
ns
TIMING SPECIFICATIONS
ADS8353
730
ns
tCONV
Conversion time
ADS7853
450
ns
ADS7253
450
ns
8.5.3.2.3
16-CLK, Dual-SDO Mode (CFR.B11 = 1, CFR.B10 = 0)
The 16-CLK, dual-SDO mode is designed to support the maximum throughput at lower SCLK frequencies. This
interface mode is not supported by the ADS8353.
For the ADS7853 and ADS7253, this interface mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 0.
In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B
conversion result. Figure 93 shows a detailed timing diagram for this mode.
Figure 93. 16-CLK, Dual-SDO Mode Timing Diagram
42
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Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: ADS8353 ADS7853 ADS7253



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