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ADS7253IPW 数据表(PDF) 40 Page - Texas Instruments |
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ADS7253IPW 数据表(HTML) 40 Page - Texas Instruments |
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40 / 71 page  ADS8353, ADS7853, ADS7253 SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014 www.ti.com A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins. The device converts the sampled analog input during the conversion time (tCONV). SDO_A and SDO_B read 0 during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode. The device outputs the MSBs of ADC_A and ADC_B on SDO_A and SDO_B pins, respectively, on the 16th SCLK falling edge. The subsequent SCLK falling edges are used to shift out the rest of the bits of the conversion result, as shown in Table 12. Table 12. Data Launch Edge LAUNCH EDGE DEVICE PINS CS SCLK CS ↓ ↓1 — ↓15 ↓16 — ↓27 ↓28 ↓29 ↓30 ↓31 ↓32 ... ↑ SDO-A 0 0 — 0 D15_A — D4_A D3_A D2_A D1_A D0_A 0 ... Hi-Z ADS8353 SDO-B 0 0 — 0 D15_B — D4_B D3_B D2_B D1_B D0_B 0 ... Hi-Z SDO-A 0 0 — 0 D13_A — D2_A D1_A D0_A 0 0 0 ... Hi-Z ADS7853 SDO-B 0 0 — 0 D13_B — D2_B D1_B D0_B 0 0 0 ... Hi-Z SDO-A 0 0 — 0 D11_A — D0_A 0 0 0 0 0 ... Hi-Z ADS7253 SDO-B 0 0 — 0 D11_B — D0_B 0 0 0 0 0 ... Hi-Z In this mode, at least 32 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state. Refer to Table 13 for timing specifications specific to this serial interface mode. Table 13. 32-CLK, Dual-SDO Interface Specific Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMING REQUIREMENTS ADS8353 50 ns tCLK CLOCK period ADS7853 29.4 ns ADS7253 29.4 ns tACQ Acquisition time 33 × tCLK – tCONV ns TIMING SPECIFICATIONS ADS8353 730 ns tCONV Conversion time ADS7853 450 ns ADS7253 450 ns 40 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: ADS8353 ADS7853 ADS7253 |
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