ADS7253IPW datasheet(47/71 Pages) TI1

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Invalid Data

CFG settings for Frame (F+5)

Valid Data as per device configuration

CFG settings for Frame (F+6)

SCLK

SDO-A

and

SDO-B

SDI

Device in

SPD

Device exits

SPD

Frame (F+2)

Frame (F+3)

Frame (F+4)

Frame (F+5)

tPU_SPD

SCLK

SDO-A and

SDO-B

SDI

Valid Data as per device configuration

Device enters SPD

mode

Device in SPD

mode

Frame (F)

Frame (F+1)

ADS8353, ADS7853, ADS7253

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SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014

8.5.4.2 Software Power-Down (SPD) Mode

In software power-down (SPD) mode, all internal circuits (including the internal references) are powered down.

However, the contents of the REFDAC_A and REFDAC_B registers are retained.

As shown in Figure 97, to enter SPD mode, the device must be selected (by bringing CS low) and SDI must be

kept high for a minimum of 48 SCLK cycles during frame (F). The device goes to SPD on the CS rising edge

following frame (F). While in SPD mode, SDO_A and SDO_B go to 3-state irrespective of the status of the CS

signal.

To remain in SPD mode, SDI must remain high in subsequent frames.

Figure 97. Enter SPD Mode

As shown in Figure 98, to exit SPD mode, the device must be selected (by bringing CS low) and SDI must be

kept low for a minimum of 48 SCLK cycles during frame (F+3). The device starts powering-up on a CS rising

edge following frame (F+3). After frame (F+3), a delay of tPU_SPD must elapse before programming the

configuration register.

A valid write operation in frame (F+4) sets the device configuration for frame (F+5). Frame (F+4) must have at

least 48 SCLK falling edges. The output data in frame (F+4) should be discarded.

Note that N is a function of the device configuration, as described in Table 4.

Figure 98. Exit SPD Mode

Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.

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ADS7253IPW 数据表(PDF) 47 Page - Texas Instruments

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