AD9142ABCPZ datasheet(32/73 Pages) AD

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Data Sheet

AD9142A

The recommended procedure for a frame initiated FIFO reset is

as follows:

1. Configure the DAC in the desired interpolation mode

(Register 0x28[1:0]).

2. Ensure that the DACCLK and DCI are running and stable at

the clock inputs.

3. Ensure that the DLL is locked (if using DLL mode) or the

DCI clock is being sent properly (if using bypass mode).

Program Register 0x23 to the customized value, if the

desired value is not 0x40.

4. Configure the FRAME_RESET_MODE bits (Register 0x22,

Bits [1:0]) to 00b.

5. Choose whether to use continuous or one shot mode by

writing 0 or 1 to EN_CON_FRAME_RESET (Register 0x22,

Bit 2).

6. Toggle the frame input from 0 to 1 and back to 0. The pulse

width needs to be longer than the minimum requirement.

a. If the frame input is a continuous clock, turn on the

signal.

7. Read back Register 0x24 multiple times to verify that the

actual FIFO level is set to the requested level and the

readback values are stable. By design, the readback is

within ±1 DACCLK around the requested level.

Monitoring the FIFO Status

The real-time FIFO status can be monitored from the SPI

reset. Without timing drifts in the system, this readback does

not change from that which resulted from the FIFO reset. When

there is a timing drift or other abnormal clocking situation, the

FIFO level readback can change. However, as long as the FIFO

does not overflow or underflow, there is no error in data trans-

mission. Three status bits in Register 0x06, Bits[2:0], indicate if

there are FIFO underflows, overflows, or similar situations. The

status of the three bits can be latched and used to trigger

hardware interrupts, IRQ1 and IRQ2. To enable latching and

interrupts, configure the corresponding bits in Register 0x03

and Register 0x04.

Rev. A | Page 31 of 72

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