AD9142ABCPZ datasheet(41/73 Pages) AD

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AD9142A

Data Sheet

Rev. A | Page 40 of 72

INTERRUPT REQUEST OPERATION

The AD9142A provides an interrupt request output signal on

Pin 50 and Pin 51 (IRQ2 and IRQ1, respectively) that can be used

to notify an external host processor of significant device events.

Upon assertion of the interrupt, query the device to determine

the precise event that occurred. The IRQ1 pin is an open-drain,

active low output. Pull the IRQ1 pin high external to the device.

This pin can be tied to the interrupt pins of other devices with

open-drain outputs to wire-OR these pins together.

Ten event flags provide visibility into the device. These flags are

located in the two event flag registers, Register 0x05 and

selected in the interrupt enable registers, Register 0x03 and

flag latches and triggers an external interrupt. When the flag

interrupt is disabled, the event flag monitors the source signal,

but the IRQ1 and IRQ2 pins remain inactive.

INTERRUPT WORKING MECHANISM

Figure 51 shows the interrupt related circuitry and how the event

flag signals propagate to the IRQx output. The INTERRUPT_

ENABLE signal represents one bit from the interrupt enable

from the event flag register. The EVENT_FLAG_SOURCE signal

represents one of the device signals that can be monitored, such as

the PLL_LOCK signal from the PLL phase detector or the

FIFO_WARNING_1 signal from the FIFO controller.

When an interrupt enable bit is set high, the corresponding event

flag bit reflects a positively tripped version of the EVENT_FLAG_

SOURCE signal; that is, the event flag bit is latched on the rising

edge of the EVENT_FLAG_SOURCE signal. This signal also

asserts the external IRQ pins.

When an interrupt enable bit is set low, the event flag bit reflects

the present status of the EVENT_FLAG_SOURCE signal, and

the event flag has no effect on the external IRQ pins.

Clear the latched version of an event flag (the INTERRUPT_

SOURCE signal) in one of two ways. The recommended

method is by writing 1 to the corresponding event flag bit. The

second method is to use a hardware or software reset to clear the

INTERRUPT_SOURCE signal.

The IRQ2 circuitry works in the same way as the IRQ1 circuitry.

Any one or multiple event flags can be enabled to trigger the

IRQ1 and IRQ2 pins. The user can select one or both hardware

interrupt pins for the enabled event flags. Register 0x07 and

routed. Set Register 0x07 and Register 0x08 to 0 for IRQ1 and set

these registers to 1 for IRQ2.

INTERRUPT SERVICE ROUTINE

Interrupt request management starts by selecting the set of

event flags that require host intervention or monitoring. Enable

the events that require host action so that the host is notified

when they occur. For events requiring host intervention upon

IRQx activation, run the following routine to clear an interrupt

request:

Read the status of the event flag bits that are being

monitored.

Set the interrupt enable bit low so that the unlatched

EVENT_FLAG_SOURCE signal can be monitored directly.

Perform any actions that may be required to clear the

EVENT_FLAG_SOURCE signal. In many cases, no

specific actions may be required.

Read the event flag to verify that the actions taken have

cleared the EVENT_FLAG_SOURCE signal.

Clear the interrupt by writing 1 to the event flag bit.

Set the interrupt enable bits of the events to be monitored.

Note that some EVENT_FLAG_SOURCE signals are latched

signals. These signals are cleared by writing to the correspon-

ding event flag bit. For more information about each of the

event flags, see the Device Configuration Register Map section.

Figure 51. Simplified Schematic of IRQ Circuitry

INTERRUPT_ENABLE

EVENT_FLAG_SOURCE

DEVICE_RESET

EVENT_FLAG

INTERRUPT_

SOURCE

OTHER

INTERRUPT

SOURCES

IRQ

WRITE_1_TO_EVENT_FLAG

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