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AD9142ABCPZ 数据表(PDF) 52 Page - Analog Devices

部件名 AD9142ABCPZ
功能描述  Multiple chip synchronization
PDF  73 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9142ABCPZ 数据表(HTML) 52 Page - Analog Devices

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Data Sheet
AD9142A
Reg
Name
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x42
GAIN_STEP_
CTRL1
DAC_
OUTPUT_OFF
DAC_
OUTPUT_
STATUS
RAMP_DOWN_STEP
0x41 RW
0x43
TX_ENABLE_
CTRL
[7:0]
Reserved
TXENABLE_
GAINSTEP_EN
TXENABLE_
SLEEP_EN
TXENABLE_
POWER_
DOWN_EN
0x07 RW
0x44
DAC_
OUTPUT_CTRL
[7:0] DAC_
OUTPUT_
CTRL_EN
Reserved
FIFO_
WARNING_
SHUTDOWN_
EN
OVERTHRESHOLD
_SHUTDOWN_EN
Reserved
FIFO_ERROR_
SHUTDOWN_
EN
0x8D RW
0x5E
ENABLE_DLL_
DELAY_CELL0
[7:0]
DELAY_CELL_ENABLE [7:0]
0xFF
0x5F
ENABLE_DLL_
DELAY_CELL1
[7:0]
Reserved
DELAY_CELL_ENABLE [10:8]
0x67 RW
0x60
SED_CTRL
[7:0] SED_ENABLE SED_ERR_
CLEAR
AED_ENABLE SED_DEPTH
Reserved
AED_PASS
AED_FAIL
SED_FAIL
0x00 RW
0x61
SED_PATT_
L_I0
[7:0]
SED_PATTERN_RISE_I0[7:0]
0x00 RW
0x62
SED_PATT_
H_I0
[7:0]
SED_PATTERN_RISE_I0[15:8]
0x00 RW
0x63
SED_PATT_
L_Q0
[7:0]
SED_PATTERN_FALL_Q0[7:0]
0x00 RW
0x64
SED_PATT_
H_Q0
[7:0]
SED_PATTERN_FALL_Q0[15:8]
0x00 RW
0x65
SED_PATT_
L_I1
[7:0]
SED_PATTERN_RISE_I1[7:0]
0x00 RW
0x66
SED_PATT_
H_I1
[7:0]
SED_PATTERN_RISE_I1[15:8]
0x00 RW
0x67
SED_PATT_
L_Q1
[7:0]
SED_PATTERN_FALL_Q1[7:0]
0x00 RW
0x68
SED_PATT_
H_Q1
[7:0]
SED_PATTERN_FALL_Q1[15:8]
0x00 RW
0x6A
PARITY_CTRL
[7:0] PARITY_
ENABLE
PARITY_EVEN PARITY_ERR
CLEAR
Reserved
PARERRFAL
PARERRIS
0x00 RW
0x6B
PARITY_ERR_
RISING
[7:0]
Parity Rising Edge Error Count
0x00 R
0x6C
PARITY_ERR_
FALLING
[7:0]
Parity Falling Edge Error Count
0x00 R
0x7F
Version
[7:0]
Version
0x0B R
Rev. A | Page 51 of 72



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