AD9142ABCPZ datasheet(14/73 Pages) AD

14 / 73 page

Data Sheet

AD9142A

Pin No.

Mnemonic

Description

D9P

Data Bit 9, Positive.

D9N

Data Bit 9, Negative.

D8P

Data Bit 8, Positive.

D8N

Data Bit 8, Negative.

DCIP

Data Clock Input, Positive.

DCIN

Data Clock Input, Negative.

D7P

Data Bit 7, Positive.

D7N

Data Bit 7, Negative.

D6P

Data Bit 6, Positive.

D6N

Data Bit 6, Negative.

D5P

Data Bit 5, Positive.

D5N

Data Bit 5, Negative.

DVDD18

1.8 V Digital Supply. Pin 36 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

D4P

Data Bit 4, Positive.

D4N

Data Bit 4, Negative.

D3P

Data Bit 3, Positive.

D3N

Data Bit 3, Negative.

D2P

Data Bit 2, Positive.

D2N

Data Bit 2, Negative.

DVDD18

1.8 V Digital Supply. Pin 43 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

D1P

Data Bit 1, Positive.

D1N

Data Bit 1, Negative.

D0P

Data Bit 0, Positive.

D0N

Data Bit 0, Negative.

DVDD18

1.8 V Digital Supply. Pin 48 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

DVDD18

1.8 V Digital Supply. Pin 49 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

IRQ2

Second Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18

through a 10 kΩ resistor.

IRQ1

First Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through

a 10 kΩ resistor.

SDIO

Serial Port Data Input/Output. CMOS levels with respect to DVDD18.

SCLK

Serial Port Clock Input. CMOS levels with respect to DVDD18.

Serial Port Chip Select. Active low (CMOS levels with respect to DVDD18).

AVDD33

3.3 V Analog Supply.

IOUT2P

QDAC Positive Current Output.

IOUT2N

QDAC Negative Current Output.

AVDD33

3.3 V Analog Supply.

CVDD18

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

CVDD18

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

DACCLKN

DAC Clock Input, Negative.

DACCLKP

DAC Clock Input, Positive.

CVDD18

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

CVDD18

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

AVDD33

3.3 V Analog Supply.

IOUT1N

IDAC Negative Current Output.

IOUT1P

IDAC Positive Current Output.

AVDD33

3.3 V Analog Supply.

FSADJ

Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to GND.

VREF

Voltage Reference. Nominally 1.2 V output. Decouple VREF to GND.

Rev. A | Page 13 of 72

AD9142ABCPZ 数据表(PDF) 14 Page - Analog Devices

AD9142ABCPZ 数据表(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表下载

链接网址

AD9142ABCPZ 数据表(PDF) 14 Page - Analog Devices

AD9142ABCPZ 数据表(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表 下载

链接网址

数据表下载