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AD9142ABCPZ 数据表(PDF) 50 Page - Analog Devices |
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AD9142ABCPZ 数据表(HTML) 50 Page - Analog Devices |
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50 / 73 page  Data Sheet AD9142A DEVICE CONFIGURATION REGISTER MAP Table 25. Device Configuration Register Map Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x00 Common [7:0] Reserved SPI_LSB_ FIRST DEVICE_ RESET Reserved 0x00 RW 0x01 PD_CONTROL [7:0] PD_IDAC PD_QDAC PD_DATARCV Reserved PD_DEVICE PD_DACCLK PD_FRAME 0xC0 RW 0x03 INTERRUPT_ ENABLE0 [7:0] Reserved ENABLE_ SYNC_LOST ENABLE_ SYNC_ LOCKED ENABLE_ SYNC_DONE ENABLE_PLL_ LOST ENABLE_PLL_ LOCKED ENABLE_ OVER_ THRESHOLD ENABLE_ DACOUT_ MUTED 0x00 RW 0x04 INTERRUPT_ ENABLE1 [7:0] ENABLE_ PARITY_FAIL ENABLE_ SED_FAIL ENABLE_DLL_ WARNING ENABLE_ DLL_LOCKED Reserved ENABLE_FIFO_ UNDERFLOW ENABLE_ FIFO_ OVERFLOW ENABLE_ FIFO_ WARNING 0x00 RW 0x05 INTERRUPT_ FLAG0 [7:0] Reserved SYNC_LOST SYNC_ LOCKED SYNC_DONE PLL_LOST PLL_LOCKED OVER_ THRESHOLD DACOUT_ MUTED 0x00 R 0x06 INTERRUPT_ FLAG1 [7:0] PARITY_FAIL SED_FAIL DLL_ WARNING DLL_LOCKED Reserved FIFO_ UNDERFLOW FIFO_ OVERFLOW FIFO_ WARNING 0x00 R 0x07 IRQ_SEL0 [7:0] Reserved SEL_SYNC_ LOST SEL_SYNC_ LOCKED SEL_SYNC_ DONE SEL_PLL_LOST SEL_PLL_ LOCKED SEL_OVER_ THRESHOLD SEL_ DACOUT_ MUTED 0x00 RW 0x08 IRQ_SEL1 [7:0] SEL_PARITY_ FAIL SEL_SED_ FAIL SEL_DLL_ WARNING SEL_DLL_ LOCKED Reserved SEL_FIFO_ UNDERFLOW SEL_FIFO_ OVERFLOW SEL_FIFO_ WARNING 0x00 RW 0x09 FRAME_ MODE [7:0] Reserved PARUSAGE FRMUSAGE Reserved FRAME_PIN_USAGE 0x00 RW 0x0A DATA_CNTR_0 [7:0] DLL_ENABLE DUTY_ CORRECTION_ ENABLE Reserved DLL_PHASE_OFFSET 0x40 RW 0x0B DATA_CNTR_1 [7:0] CLEAR_WARN Reserved 0x39 RW 0x0C DATA_CNTR_2 [7:0] Reserved 0x64 RW 0x0D DATA_CNTR_3 [7:0] LOW_DCI_EN Reserved DC_COUPLE_ LOW_EN Reserved 0x06 RW 0x0E DATA_STAT_0 [7:0] DLL_LOCK DLL_WARN DLL_START_ WARNING DLL_END_ WARNING Reserved DCI_ON Reserved DLL_ RUNNING 0x00 R 0x10 DACCLK_ RECEIVER_ CTRL [7:0] DACCLK_ DUTYCYCLE_ CORRECTION Reserved DACCLK_ CROSSPOINT_ CTRL_ENABLE DACCLK_CROSSPOINT_LEVEL 0xFF RW 0x11 REFCLK_ RECEIVER_ CTRL [7:0] DUTYCYCLE_ CORRECTION Reserved REFCLK_ CROSSPOINT_ CTRL_ENABLE REFCLK_CROSSPOINT_LEVEL 0x5F RW 0x12 PLL_CTRL0 [7:0] PLL_ENABLE AUTO_ MANUAL_ SEL PLL_MANUAL_BAND 0x00 RW 0x14 PLL_CTRL2 [7:0] PLL_LOOP_BW PLL_CP_CURRENT 0xE7 RW 0x15 PLL_CTRL3 [7:0] DIGLOGIC_DIVIDER Reserved CROSSPOINT_ CTRL_EN VCO_DIVIDER LOOP_DIVIDER 0xC9 RW 0x16 PLL_STATUS0 [7:0] PLL_LOCK Reserved VCO_CTRL_VOLTAGE_READBACK 0x00 R 0x17 PLL_STATUS1 [7:0] Reserved PLL_BAND_READBACK 0x00 R 0x18 IDAC_FS_ ADJ0 [7:0] IDAC_FULLSCALE_ADJUST_LSB 0xF9 RW 0x19 IDAC_FS_ ADJ1 [7:0] Reserved IDAC_FULLSCALE_ADJUST_ MSB 0xE1 RW 0x1A QDAC_FS_ADJ0 [7:0] QDAC_FULLSCALE_ADJUST_LSB 0xF9 RW 0x1B QDAC_FS_ADJ1 [7:0] Reserved QDAC_FULLSCALE_ADJUST_ MSB 0x01 RW 0x1C DIE_TEMP_ SENSOR_CTRL [7:0] Reserved FS_CURRENT REF_CURRENT DIE_TEMP_ SENSOR_EN 0x02 RW 0x1D DIE_TEMP_ LSB [7:0] DIE_TEMP_LSB 0x00 R 0x1E DIE_TEMP_ MSB [7:0] DIE_TEMP_MSB 0x00 R 0x1F CHIP_ID [7:0] CHIP_ID 0x0A R 0x20 INTERRUPT_ CONFIG [7:0] INTERRUPT_CONFIGURATION 0x00 RW 0x21 SYNC_CTRL [7:0] Reserved SYNC_CLK_ EDGE_SEL SYNC_ ENABLE 0x00 RW 0x22 FRAME_RST_ CTRL [7:0] Reserved ARM_FRAME EN_CON_ FRAME_RESET FRAME_RESET_MODE 0x12 RW Rev. A | Page 49 of 72 |
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