 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AD9142ABCPZ 数据表(PDF) 65 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9142ABCPZ 数据表(HTML) 65 Page - Analog Devices |
|
|
65 / 73 page  AD9142A Data Sheet NCO FREQUENCY TUNING WORD 3 REGISTER Address: 0x34, Reset: 0x10, Name: NCO_FREQ_TUNING_WORD3 Table 73. Bit Descriptions for NCO_FREQ_TUNING_WORD3 Bits Bit Name Settings Description Reset Access [7:0] NCO_FTW3 Bits[7:0] together with the bits in Register 0x31 through Register 0x33 form the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when a serial port update or frame update is initialized in Register 0x30. It is in twos complement format. 0x10 RW NCO PHASE OFFSET 0 REGISTER Address: 0x35, Reset: 0x00, Name: NCO_PHASE_OFFSET0 Table 74. Bit Descriptions for NCO_PHASE_OFFSET0 Bits Bit Name Settings Description Reset Access [7:0] NCO_PHASE_OFFSET_LSB This register, together with Register 0x36, sets the initial phase of the complex carrier signal upon reset. The phase offset spans from 0° to 360°. Each bit represents an offset of 0.0055°. This value is in twos complement format. 0x00 RW NCO PHASE OFFSET 1 REGISTER Address: 0x36, Reset: 0x00, Name: NCO_PHASE_OFFSET1 Table 75. Bit Descriptions for NCO_PHASE_OFFSET1 Bits Bit Name Settings Description Reset Access [7:0] NCO_PHASE_OFFSET_MSB This register, together with Register 0x35, sets the initial phase of the complex carrier signal upon reset. The phase offset spans from 0° to 360°. Each bit represents an offset of 0.0055°. This value is in twos complement format. 0x00 RW IQ PHASE ADJUST 0 REGISTER Address: 0x37, Reset: 0x00, Name: IQ_PHASE_ADJ0 Table 76. Bit Descriptions for IQ_PHASE_ADJ0 Bits Bit Name Settings Description Reset Access [7:0] IQ_PHASE_ADJ_LSB Q phase adjust, Bits[7:0] along with Bits[4:0] in Register 0x38, is used to insert a phase offset between the I and Q datapaths. It provides an adjustment range of ±14° with a step of 0.0035°. This value is in twos complement. See the Quadrature Phase Adjustment section for more information. 0x00 RW IQ PHASE ADJUST 1 REGISTER Address: 0x38, Reset: 0x00, Name: IQ_PHASE_ADJ1 Table 77. Bit Descriptions for IQ_PHASE_ADJ1 Bits Bit Name Settings Description Reset Access [4:0] IQ_PHASE_ADJ_MSB IQ phase adjust, Bits[4:0] along with Bits[7:0] in Register 0x37, is used to insert a phase offset between the I and Q datapaths. It provides an adjustment range of ±14° with a step of 0.0035°. This value is in twos complement. See the Quadrature Phase Adjustment section for more information. 0x0 RW Rev. A | Page 64 of 72 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
