AD9142ABCPZ datasheet(24/73 Pages) AD

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Data Sheet

AD9142A

DATA INTERFACE

LVDS INPUT DATA PORTS

The AD9142A has a 16-bit LVDS bus that accepts 16-bit I and

Q data either in word (16-bit) or byte (8-bit) formats. In the

word interface mode, the data is sent over the entire 16-bit data

bus. In the byte interface mode, the data is sent over the lower

8-bit (D7 to D0) LVDS bus. Table 11 lists the pin assignment of

the bus and the SPI register configuration for each mode.

Table 11. LVDS Input Data Modes

Interface Mode

Pin Assignment

SPI Register Configuration

Word

D15 to D0

Byte

D7 to D0

WORD INTERFACE MODE

In word interface mode, the digital clock input (DCI) signal is a

reference bit that generates a double data rate (DDR) data

sampling clock. Time align the DCI signal with the data. The

IDAC data follows the rising edge of the DCI, and the QDAC

data follows the falling edge of the DCI, as shown in Figure 33.

Figure 33. Timing Diagram for Word Interface Mode

BYTE INTERFACE MODE

In byte interface mode, the required sequence of the input data

stream is I[15:8], I[7:0], Q[15:8], Q[7:0]. A frame signal is

required to align the order of input data bytes properly. Time

align both the DCI signal and frame signal with the data. The

rising edge of the frame indicates the start of the sequence. The

frame can be either a one shot or periodical signal as long as its

first rising edge is correctly captured by the device. For a one

shot frame, the frame pulse must be held at high for at least one

DCI cycle. For a periodical frame, the frequency needs to be

fDCI/(2 × n)

where n is a positive integer, that is, 1, 2, 3, …

Figure 34 is an example of signal timing in byte mode.

Figure 34. Timing Diagram for Byte Interface Mode

DATA INTERFACE CONFIGURATION OPTIONS

To provide more flexibility for the data interface, some

additional options are listed in Table 12.

Table 12. Data Interface Configuration Options

Description

DATA_FORMAT (Bit 7)

Select between binary and twos

complement formats.

DATA_PAIRING (Bit 6)

Indicate I/Q data pairing on data input.

This allows the I and Q data that is

received to be paired in various ways.

DATA_BUS_INVERT (Bit 5)

Swaps the bit order of the data input

port. Remaps the input data from

D[15:0] to D[0:15].

DLL INTERFACE MODE

A source synchronous LVDS interface is used between the data

host and AD9142A to achieve high data rates while simplifying

the interface. The FPGA or ASIC feeds the AD9142A with 16-bit

input data. Along with the input data, the FPGA or ASIC

provides a DDR (double data rate) data clock input (DCI).

A delay locked loop (DLL) circuit designed to operate with DCI

clock rates between 250 and 575 MHz is used to generate a phase-

shifted version of the DCI, called DSC (data sampling clock), to

As shown in Figure 35, the DCI clock edges must be coincident

with the data bit transitions with minimum skew and jitter. The

nominal sampling point of the input data occurs in the middle

of the DCI clock edges because this point corresponds to the

center of the data eye. This is also equivalent to a nominal phase

shift of 90°of the DCI clock.

The data timing requirements are defined by a data valid

window (DVW) that is dependent on the data clock input skew,

input data jitter, and the variations of the DLL delay line across

delay settings. The DVW is defined as

DVW = tDATA PERIOD − tDATA SKEW – tDATA JITTER

The available margin for data interface timing is given by

tMARGIN = DVW − (tS + tH)

The difference between the setup and hold times, which is also

called the keep out window, or KOW, is the area where data

transitions should not happen. The timing margin allows

tuning of the DLL delay setting by the user, see Figure 36.

From the figure, it can be seen that the ideal location for the

DSC signal is 90° out of phase from the DCI input. However,

due to skew of the DCI relative to the data, it may be necessary

to change the DSC phase offset to sample the data at the center

of its eye diagram. The sampling instance can be varied in discrete

increments by offsetting the nominal DLL phase shift value of

90° via Register 0x0A, Bits[3:0]. This register is a signed value.

The MSB is the sign and the LSBs are the magnitude. The

following equation defines the phase offset relationship:

Phase Offset = 90° ± n × 11.25°, |n| < 7

where n is the DLL phase offset setting.

WORD INTERFACE MODE

DCI

INPUT DATA[15:0]

I0[15:8]

I0[7:0]

Q0[15:8]

Q0[7:0]

BYTE INTERFACE MODE

DCI

FRAME

INPUT DATA[7:0]

Rev. A | Page 23 of 72

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