AD9142ABCPZ datasheet(25/73 Pages) AD

25 / 73 page

AD9142A

Data Sheet

Figure 35 shows the DSC setup and hold times with respect to

the DCI signal and data signals.

Figure 35. LVDS Data Port Setup and Hold Times

Table 13 lists the values that are guaranteed over the operating

conditions. These values were taken with a 50% duty cycle and a

DCI swing of 450 mV p-p. For best performance, the duty cycle

variation should be kept below ±5%, and the DCI input should

be as high as possible, up to 1200 mV p-p.

Table 13. DLL Phase Setup and Hold Times (Guaranteed)

Frequency,

fDCI (MHz)

Time (ps)

Data Port Setup and Hold Times (ps)

at DLL Phase

−3

307

−125

−385

−695

834

1120

1417

368

−70

−305

−534

753

967

1207

491

−81

−245

−402

601

762

928

Figure 36. LVDS Data Port Timing Requirements

DCI

DATA

DSC

INPUT DATA

DCI

DATA EYE

DATA SAMPLE CLOCK

INPUT DATA

DCI

DATA SAMPLE CLOCK

DATA EYE

DLL PHASE

DELAY

tDATA JITTER

tH AND tS

tDCI SKEW

tDATA PERIOD

Rev. A | Page 24 of 72

AD9142ABCPZ 数据表(PDF) 25 Page - Analog Devices

AD9142ABCPZ 数据表(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表下载