AD9142ABCPZ datasheet(22/73 Pages) AD

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Data Sheet

AD9142A

SERIAL PORT OPERATION

The serial port is a flexible, synchronous serial communications

port that allows easy interfacing to many industry standard micro-

controllers and microprocessors. The serial I/O is compatible

with most synchronous transfer formats, including both the

Motorola® SPI and Intel® SSR protocols. The interface allows

read/write access to all registers that configure the AD9142A.

MSB-first or LSB-first transfer formats are supported. The serial

port interface is a 3-wire only interface. The input and output

share a single pin input/output (SDIO).

Figure 28. Serial Port Interface Pins

There are two phases to a communication cycle with the AD9142A.

Phase 1 is the instruction cycle (the writing of an instruction

byte into the device), coincident with the first 16 SCLK rising

edges. The instruction word provides the serial port controller

with information regarding the data transfer cycle, Phase 2, of

the communication cycle. The Phase 1 instruction word defines

whether the upcoming data transfer is a read or write, along with

the starting register address for the next data transfer in the

cycle.

A logic high on the CS pin, followed by a logic low, resets the

serial port timing to the initial state of the instruction cycle.

From this state, the next 16 rising SCLK edges represent the

instruction bits of the current I/O operation.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and

the system controller. Phase 2 of the communication cycle is a

transfer of one data byte. Registers change immediately upon

writing to the last bit of each transfer byte, except for the frequency

tuning word and NCO phase offsets, which change only when

the frequency tuning word (FTW) update bit is set.

DATA FORMAT

The instruction byte contains the information shown in Table 10.

Table 10. Serial Port Instruction Word

I15 (MSB)

I[14:0]

R/W

A[14:0]

R/W (Bit 15 of the instruction word) determines whether a read

or a write data transfer occurs after the instruction word write.

Logic 1 indicates a read operation and Logic 0 indicates a write

operation.

A14 to A0 (Bit 14 to Bit 0 of the instruction word) determine

the register that is accessed during the data transfer portion of

the communication cycle. For multibyte transfers, A14 is the

starting address; the device generates the remaining register

addresses based on the SPI_LSB_FIRST bit.

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device

and runs the internal state machines. The maximum frequency

of SCLK is 40 MHz. All data input is registered on the rising edge

of SCLK. All data is driven out on the falling edge of SCLK.

Chip Select (CS)

CS is an active low input that starts and gates a communication

cycle. It allows more than one device to be used on the same serial

communications line. The SDIO pins enter a high impedance

state when the CS input is high. During the communication

cycle, CS should stay low.

Serial Data I/O (SDIO)

The SDIO pin is a bidirectional data line.

SERIAL PORT OPTIONS

The serial port can support both MSB-first and LSB-first data

formats. This functionality is controlled by the SPI_LSB_FIRST bit

(Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0).

When SPI_LSB_FIRST = 0 (MSB first), the instruction and data

bits must be written from MSB to LSB. Multibyte data transfers

in MSB-first format start with an instruction word that includes the

bytes must follow from high address to low address. In MSB-first

mode, the serial port internal word address generator decrements

for each data byte of the multibyte communication cycle.

When SPI_LSB_FIRST = 1 (LSB first), the instruction and data

bits must be written from LSB to MSB. Multibyte data transfers

in LSB-first format start with an instruction word that includes the

bytes must follow from low address to high address. In LSB-first

mode, the serial port internal word address generator increments

for each data byte of the multibyte communication cycle.

If the MSB-first mode is active, the serial port controller data

address decrements from the data address written toward 0x00

for multibyte I/O operations. If the LSB-first mode is active, the

serial port controller data address increments from the data

address written toward 0xFF for multibyte I/O operations.

SCLK

SDIO

SPI

PORT

Rev. A | Page 21 of 72

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