数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

STV3550 数据表(PDF) 59 Page - STMicroelectronics

部件名 STV3550
功能描述  LCD and Matrix Display TV Processor
PDF  144 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STV3550 数据表(HTML) 59 Page - STMicroelectronics

Back Button STV3550 Datasheet HTML 55Page - STMicroelectronics STV3550 Datasheet HTML 56Page - STMicroelectronics STV3550 Datasheet HTML 57Page - STMicroelectronics STV3550 Datasheet HTML 58Page - STMicroelectronics STV3550 Datasheet HTML 59Page - STMicroelectronics STV3550 Datasheet HTML 60Page - STMicroelectronics STV3550 Datasheet HTML 61Page - STMicroelectronics STV3550 Datasheet HTML 62Page - STMicroelectronics STV3550 Datasheet HTML 63Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 59 / 144 page
background image
STV3550
59/144
5.2
Gamma Correction
The Gamma correction is a completely programmable block, which is used to correct the input
pixels. The CPU supplies the gamma correction curves by writing the data into the Look Up Tables
located in this block. This block can be bypassed, in which case the flow of pixels is left unchanged.
5.3
Perfect Color Engine
PCE (Perfect Color Engine) dithers an input 10 bit video stream down to 4-6-8-10 output bits.The
dithering is done in space and time in such a way that the eye does not perceive objectionable
artifacts such as:
Fixed dither patterns
Contours
Flickering pixels
Phase correlated flickering, which creates wave patterns known as swimming.
Note:
The dithering efffect tends to average neighboring pixels and smooth the color tonal transition and
contours of the image. It works by spreading the quantization error over neighboring pixels (spatially
and temporally).
5.4
Digital Video Output Stage
5.4.1
Introduction
This block performs the digital video output stage. This block generates the Data Enable (DE) signal
on account of the register configuration, it also resynchronises and recalibrates the Vsync and
Hsync signals according to the register configuration. This block delivers the Data Clock (Dclk) with
a delay selected by the register and fixes the default output state of all the digital video interface.
This block also provide a reduce interface with a data valid on each edge of the clock.
The output frequency range is 22MHz up to 72MHz according to the user configuration.
Figure 42: Gamma Correction Block Diagram
Blue LUT
Green LUT
Pixel
outputs
Red LUT
STBus
STBus
Interface
(STI)
Pixel Inputs
Translation (TRA)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com