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STV3550 数据表(PDF) 85 Page - STMicroelectronics |
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STV3550 数据表(HTML) 85 Page - STMicroelectronics |
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85 / 144 page  CPU and System Management Functional Description STV3550 85/144 6.8 Clock Generator The chip includes different asynchronous clock domains. In general, each block connected to the Interconnect has two clock domains separated by a FIFO: the input or output clock domain and the Interconnect clock domain. The different clocks are generated by an on-chip clock synthesizer based on a 27 MHz reference clock. This can be the incoming D1 clock or a fixed external clock. All clocks are then referenced to the master clock. See Figure 55. Note: 1 The pixel clock can be a free-running 22 to 72 MHz clock issued from a synthesizer. The pixel clock is obtained by a division of the DAC clock signal. 2 A second possibility is to have the pixel clock locked on the front-end clock (D1), through the synthesizer, used as PLL. The time constant is adjustable by programming. 3 All the other clocks are generated by a high frequency P/Q PLL, locked to the crystal oscillator. Line-locked PLL 1 1 TOTAL 562531 7 2 Figure 55: Clock Frequency Domains Table 21: Interrupt Sources (page 2 of 2) Interrupt Source Name Number of Interrupts Number of Synchronous Interrupts Number of Asynchronous Interrupts Number of Wake-up Interrupts Off-chip Interrupts Build-Up YSI/CTI Video ST20 Core H100 R G B SDRAM SDIN TNR HV Filter 8 16/32 TV Peripherals 30 I/Os Flash Counter NRESET Clock Generator 2D Block Move OSD Pipeline Pipeline Block Time Base Generator TV Chassis Control CSA Picture Comp. Cursor BG Plane EMI Compositor V100 27 MHz 27 MHz 81 MHz 22 to 72 MHz 22 to 72 MHz 4 to 100 MHz 100 MHz 44 to 72 MHz 44 to 72 MHz 4 to 100 MHz 27 MHz YCRCB[7:0] CLK_DATA HSYNC VSYNC EXTALIN 27 MHz Gamma Digital Video Output Perfect Color Engine Correction |
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