STV3550 datasheet(89/144 Pages) STMICROELECTRONICS

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7.3

Watchdog Timer (WDT)

The Watchdog Timer (WDT) provides a fail-safe mechanism used to reset the chip if the software

fails to clear a counter within a given period.

The Watchdog Timer (WDT) has a counter which is clocked to provide up to a 2-second delay (11

bits). This counter is periodically cleared by software as described below. If the software fails to

clear the counter within the timeout period, a “watchdog reset” signal is generated to reset the chip.

The counter is in the CLK_RTC clock domain.

A timeout register is used to configure the watchdog delay. The transfer occurs at the next clear of

the timer.

A status flag is set by a watchdog reset. This can be used to indicate to application code that the

system was reset by the watchdog timer. This status bit is reset only by the external reset input to

the chip.

The watchdog timer function is enabled by a control bit. If this bit is reset, a watchdog reset must

never occur.

The watchdog counter can be also stopped by an internal signal. When this signal is high, the

watchdog counter is stopped. This signal may be use by an emulator or a dedicated mode to stop

the watchdog activity.

Note:

The counter is described as a counter that counts from zero up to the maximum allowed number.

7.3.1

Clearing the Counter

The watchdog counter is cleared under software control. To minimize the possibility of this

happening erroneously, there are two registers which have to be written to in order to clear the

counter. Each of these must be have the correct values (0xA and 0x5, respectively) written to them

to clear the counter.

The command registers themselves are cleared by:

●

a successful software clear of the counter,

●

writing the incorrect value to either of the registers,

●

triggering a watchdog reset.

Figure 57: Watchdog Timer Behavior

Watchdog

Counter

Time

Value

notRST

Software Clears Watchdog

Software

Fails

Watchdog

Reset

Generated

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