STV3550 datasheet(97/144 Pages) STMICROELECTRONICS

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7.7

Inter Integrated Circuit Bus (I²C)

The SSC2 is a high-speed synchronous serial interface which can be used to interface to a wide

variety of serial memories, remote control receivers, and other microcontrollers.

There are a number of serial interface standards for these. The SSC2 supports the I²C bus. The

general programmable features should also allow it to interface to other serial bus standards.

The SSC2 supports full-duplex and half-duplex synchronous communication when used in

conjunction with the PIO for output and input pad control.

It uses a 2 PIO pad interface: serial clock “SCLK”, serial data in/out “SDA”. These PIO pads are

connected to the SSC2 clock/data interface pins in a configuration which allows their direction to be

changed when in master or slave mode (see Section 7.7.3: PIO Pad Connection & Control).

The serial clock signal is either generated by the SSC2 (in master mode) or received from an

external master (in slave mode). The output and input data is synchronized to the serial clock.

The following features are programmable: baud rate, data width, shift direction (heading control),

clock polarity and clock phase.

The I²C features include: multi-master arbitration, acknowledge generation, start/stop condition

generation/detection and clock stretching. These allow software to fully implement all aspects of the

standard e.g. master and slave mode, multi-master mode, 10 bit addressing and fast mode.

7.7.1

Basic Features

Each STV3550 I2C cell has the following features:

●

Possibility of swapping SCL and SDA lines,

●

Selection one SCL, SDA couple between two choices,

●

Each STV3550 I²C cell can be connected to four I²C buses.

7.7.2

Functional Description

The basic architecture of the SSC2 is shown in Figure 62.

Control of the direction, as an input, output or bi-directional, of the SCL and SDA pins is done in

software by configuring the PIO pads.

The SSC2 itself has clock in/out and data in/out pins for connection to all 2 pads and a pin control

block which selects the relevant data input and output according to the master or slave mode set

(see Section 7.7.3: PIO Pad Connection & Control).

The serial_clock_out signal is programmable in master mode for baud rate, polarity and phase. This

is described in Section 7.7.4: Clock Generation.

The SSC2 works by taking the data frame (2 to 16 bits) from a transmission buffer and placing it into

a shift register. It then shifts the data at the serial_clock frequency out of the serial_data_out pin and

synchronously shifts in data coming from the serial_data_in pin. The number of bits and the

direction of shifting (MSB or LSB first) are programmable. This is described in Section 7.7.6: Shift

After the data frame has been completely shifted out of the shift register it transfers the received

data frame into the receive buffer. The transmit and receive buffers are described in Section

7.7.9: Transmit & Receive Buffers.

The SSC2 is therefore double buffered. This allows back-to-back transmission and reception of

data frames up to the speed that interrupts can be serviced.

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