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STV3550 数据表(PDF) 64 Page - STMicroelectronics |
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STV3550 数据表(HTML) 64 Page - STMicroelectronics |
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64 / 144 page  64/144 STV3550 5.4.6 Data Enable Output This signal is fully generated according to the control register value. The user must assume the video window is correct according to the display data (video + OSD + background). The Data Enable signal is in the clk_dac domain. This signal generates a jitter free signal only if the Hsync and Vsync signal are output in the same clock domain (‘clk_dac’). The reference signals to generate this signal are hs_pix, vs_rst_100_pix and lineupcnt_pix. We could select the DE polarity with a dedicated register. 22 P24 000 0 26 P25 000 0 27 P26 000 0 28 P27 000 0 29 P28 000 0 30 P29 000 0 Table 18: Multiplex Output STV3550 Pin Number STV3550 Pad Multiplex Output 3x10bits Phase 0 Multiplex Output 3x10 bits Phase 1 Multiplex Output 3x8 bits Phase 0 Multiplex Output 3x8 bits Phase 1 line 0 start line display line 10 bits 10 bits |
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